865 commits

Author	SHA1	Message	Date
Eddie Hung	d910bec8e0	Update xc7/xcu bram rules	2019-12-16 13:00:58 -08:00
Eddie Hung	5d00996426	Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram	2019-12-16 12:06:47 -08:00
Eddie Hung	7545ab3814	Populate DID/DOD even if unused	2019-12-16 11:57:04 -08:00
Eddie Hung	c4d37813cb	Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q	2019-12-16 10:41:13 -08:00
Diego H	f3f59910eb	Removing fixed attribute value to !ramstyle rules	2019-12-15 23:51:58 -06:00
Diego H	b35559fc33	Merging attribute rules into a single match block; Adding tests	2019-12-15 23:33:09 -06:00
Diego H	266993408a	Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific	2019-12-13 15:43:24 -06:00
Eddie Hung	52875b0d61	Merge pull request #1533 from dh73/bram_xilinx ... Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1	2019-12-13 12:01:03 -08:00
Eddie Hung	c3262d6075	Disable RAM16X1D match rule; carry-over from LUT4 arches	2019-12-13 08:59:17 -08:00
Eddie Hung	d6514fc2e1	RAM64M8 to also have [5:0] for address	2019-12-13 08:54:19 -08:00
Eddie Hung	dd7d2d8db6	Duplicate tribuf call, credit to @mwkmwkmwk	2019-12-13 08:51:05 -08:00
Eddie Hung	8925bf4b96	Add RAM32X6SDP and RAM64X3SDP modes	2019-12-12 18:52:28 -08:00
Eddie Hung	50e0c83560	Fix RAM64M model to have 6 bit address bus	2019-12-12 18:52:03 -08:00
Eddie Hung	7a9d1be97d	Add memory rules for RAM16X1D, RAM32M, RAM64M	2019-12-12 17:44:59 -08:00
Diego H	751a18d7e9	Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.	2019-12-12 17:32:58 -06:00
Eddie Hung	9ab1feeaf1	abc9_map.v: fix Xilinx LUTRAM	2019-12-12 14:56:52 -08:00
Eddie Hung	3eed8835b5	abc9_map.v: fix Xilinx LUTRAM	2019-12-12 14:56:15 -08:00
Eddie Hung	3bd623bb05	synth_xilinx: error out if tristate without '-iopad'	2019-12-12 14:33:33 -08:00
Diego H	937ec1ee78	Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1	2019-12-12 13:50:36 -06:00
Diego H	ab6ac8327f	Merge https://github.com/YosysHQ/yosys into bram_xilinx	2019-12-12 13:40:05 -06:00
Eddie Hung	49c2e59b2a	Fix comment	2019-12-09 15:44:19 -08:00
Eddie Hung	a46a7e8a67	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-12-06 23:22:52 -08:00
Eddie Hung	98c9ea605b	techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger	2019-12-06 17:05:02 -08:00
Eddie Hung	c767525441	Remove creation of $abc9_control_wire	2019-12-06 16:23:09 -08:00
Eddie Hung	ec0acc9f85	abc9 to use mergeability class to differentiate sync/async	2019-12-06 00:12:37 -08:00
Eddie Hung	02786b0aa0	Remove clkpart	2019-12-05 17:25:26 -08:00
Eddie Hung	864bff14f1	Revert "Special abc9_clock wire to contain only clock signal" ... This reverts commit 6a2eb5d8f9.	2019-12-05 11:11:53 -08:00
Eddie Hung	0d248dd7ba	Missing wire declaration	2019-12-04 23:04:40 -08:00
Eddie Hung	19bc429482	abc9_map.v to transform INIT=1 to INIT=0	2019-12-04 21:36:41 -08:00
Eddie Hung	258a34e6f1	Oh deary me	2019-12-04 20:33:24 -08:00
Eddie Hung	b43986c5a1	output reg Q -> output Q to suppress warning	2019-12-04 16:34:34 -08:00
Eddie Hung	31ef4cc704	abc9_map.v to do `zinit' and make INIT = 1'b0	2019-12-04 16:11:02 -08:00
Marcin Kościelnicki	fcce94010f	xilinx: Add tristate buffer mapping. (#1528) ... Fixes #1225.	2019-12-04 09:44:00 +01:00
Marcin Kościelnicki	10014e2643	xilinx: Add models for LUTRAM cells. (#1537)	2019-12-04 06:31:09 +01:00
Eddie Hung	a181ff66d3	Add abc9_init wire, attach to abc9_flop cell	2019-12-03 18:47:09 -08:00
Eddie Hung	f98aa1c13f	Revert "Add INIT value to abc9_control" ... This reverts commit 19bfb41958.	2019-12-03 15:40:44 -08:00
Eddie Hung	0add5965c7	techmap abc_unmap.v before xilinx_srl -fixed	2019-12-03 14:27:45 -08:00
Eddie Hung	19bfb41958	Add INIT value to abc9_control	2019-12-02 14:17:06 -08:00
Marcin Kościelnicki	2badaa9adb	xilinx: Add missing blackbox cell for BUFPLL.	2019-11-29 16:56:27 +01:00
Eddie Hung	b1ab7c16c4	clkpart -unpart into 'finalize'	2019-11-28 12:59:43 -08:00
Diego H	3a5a65829c	Adjusting Vivado's BRAM min bits threshold for RAMB18E1	2019-11-27 12:05:04 -06:00
Eddie Hung	df8dc6d1fb	ean call after abc{,9}	2019-11-27 09:10:34 -08:00
Eddie Hung	f6c0ec1d09	Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff	2019-11-27 01:03:33 -08:00
Eddie Hung	739f530906	Move 'clean' from map_luts to finalize	2019-11-26 14:51:39 -08:00
Marcin Kościelnicki	0466c48533	xilinx: Add simulation models for IOBUF and OBUFT.	2019-11-26 08:15:20 +01:00
Eddie Hung	d087024caf	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-25 12:42:09 -08:00
Eddie Hung	6a2eb5d8f9	Special abc9_clock wire to contain only clock signal	2019-11-25 12:36:13 -08:00
Marcin Kościelnicki	6cdea425b8	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
Marcin Kościelnicki	7562e7304e	xilinx: Use INV instead of LUT1 when applicable	2019-11-25 20:40:39 +01:00
Eddie Hung	eb11c06a69	For abc9, run clkpart before ff_map and after abc9	2019-11-23 10:18:22 -08:00