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Author	SHA1	Message	Date
Clifford Wolf	90d8329f64	Improve Verific SVA import: negedge and $past	2017-07-27 11:40:07 +02:00
Clifford Wolf	147ff96ba3	Improve Verific SVA importer	2017-07-27 10:39:39 +02:00
Clifford Wolf	649bb9374f	Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators	2017-07-26 18:28:55 +02:00
Clifford Wolf	530040ba6f	Improve Verific bindings (mostly related to SVA)	2017-07-26 18:00:01 +02:00
Clifford Wolf	abd3b4e8e7	Improve "help verific" message	2017-07-25 15:13:22 +02:00
Clifford Wolf	6dbe1d4c92	Add "verific -extnets"	2017-07-25 14:53:11 +02:00
Clifford Wolf	493fedbaf9	Add "using std::get" to yosys.h	2017-07-25 14:52:34 +02:00
Clifford Wolf	c97c92e4ec	Improve "verific -all" handling	2017-07-25 13:33:25 +02:00
Clifford Wolf	41be530c4e	Add "verific -import -d <dump_file"	2017-07-24 13:57:16 +02:00
Clifford Wolf	92d3aad670	Add "verific -import -flatten" and "verific -import -v"	2017-07-24 11:29:06 +02:00
Clifford Wolf	84f15260b5	Add more SVA test cases for future Verific work	2017-07-22 16:35:46 +02:00
Clifford Wolf	5be535517c	Add "verific -import -k"	2017-07-22 16:16:44 +02:00
Clifford Wolf	b6bd12fade	Add error for cell output ports that are connected to constants	2017-07-22 15:08:30 +02:00
Clifford Wolf	024ba310ec	Add some simple SVA test cases for future Verific work	2017-07-22 12:31:08 +02:00
Clifford Wolf	2785aaffeb	Improve docs for verific bindings, add simply sby example	2017-07-22 11:58:51 +02:00
Clifford Wolf	b3bc7068d1	Fix handling of empty cell port assignments (i.e. ignore them)	2017-07-21 19:32:31 +02:00
Clifford Wolf	36cf18ac4c	Fix "read_blif -wideports" handling of cells with wide ports	2017-07-21 16:21:12 +02:00
Clifford Wolf	26766da343	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
Clifford Wolf	3a8f6f0f51	Add verilator support to testbenches generated by yosys-smtbmc	2017-07-21 14:33:29 +02:00
Clifford Wolf	c251e3a576	Change intptr_t to uintptr_t in hashlib.h	2017-07-18 17:38:19 +02:00
Clifford Wolf	dbb2f755c1	Merge pull request #363 from rqou/master ... Miscellaneous build tweaks	2017-07-18 15:21:12 +02:00
Robert Ou	85d667ca08	makefile: Add the option to use libtermcap	2017-07-17 14:21:59 -07:00
Robert Ou	f0741698fa	Fix build warnings for win64 ... Win64 has a 32-bit long. Use intptr_t to work on any data model.	2017-07-17 12:36:43 -07:00
Clifford Wolf	c00d8a5b73	Add $alu to list of supported cells for "stat -width"	2017-07-14 11:32:49 +02:00
Clifford Wolf	10c7709e68	Generate FSM-style testbenches in smtbmc	2017-07-12 15:57:04 +02:00
Clifford Wolf	4a8c131fa7	Fix the fixed handling of x-bits in EDIF back-end	2017-07-11 17:45:29 +02:00
Clifford Wolf	479be3cec7	Fix handling of x-bits in EDIF back-end	2017-07-11 17:38:19 +02:00
Clifford Wolf	9557fd2a36	Add attributes and parameter support to JSON front-end	2017-07-10 13:17:38 +02:00
Clifford Wolf	8a69759306	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
Clifford Wolf	4b2d1fe688	Add JSON front-end	2017-07-08 16:40:40 +02:00
Clifford Wolf	3c693b6561	Change s/asserts/assertions/ in yosys-smtbmc log messages	2017-07-07 11:52:25 +02:00
Clifford Wolf	8f7404f82c	Add "yosys-smtbmc --presat"	2017-07-07 02:47:30 +02:00
Clifford Wolf	5442554e6f	Fix generation of multiple outputs for same AIG node in write_aiger	2017-07-05 14:23:54 +02:00
Clifford Wolf	37af6294bd	Add write_table command	2017-07-05 12:13:53 +02:00
Clifford Wolf	28039c3063	Add Verific Release information to log	2017-07-04 20:01:30 +02:00
Clifford Wolf	621787a9e0	Fix some c++ clang compiler errors	2017-07-03 19:38:30 +02:00
Clifford Wolf	5c1c126374	Apply minor coding style changes to coolrunner2 target	2017-07-03 19:35:40 +02:00
Clifford Wolf	6afee022ad	Merge pull request #352 from rqou/master ... Initial Coolrunner-II support	2017-07-03 19:33:36 +02:00
Clifford Wolf	3f863c607a	Merge pull request #356 from set-soft/clean-test ... Added the test outputs to the clean target	2017-07-03 19:33:25 +02:00
Clifford Wolf	d223292aa9	Merge pull request #355 from set-soft/exclude_TBUF_merge ... Excluded $_TBUF_ from opt_merge pass	2017-07-03 19:31:59 +02:00
Salvador E. Tropea	fb30511044	Added the test outputs to the clean target	2017-07-03 13:33:11 -03:00
Salvador E. Tropea	ca23554528	Excluded $_TBUF_ from opt_merge pass	2017-07-03 13:21:20 -03:00
Clifford Wolf	3e0948e16f	Remove unneeded delays in smtbmc vlogtb	2017-07-03 15:37:17 +02:00
Clifford Wolf	287831dca3	Include output ports with constant driver in AIGER output	2017-07-03 14:53:17 +02:00
Clifford Wolf	ea805af6f5	Add "yosys-smtbmc --vlogtb-top"	2017-07-01 18:19:23 +02:00
Clifford Wolf	0a02cdb93b	Fix and_or_buffer optimization in opt_expr for signed operators	2017-07-01 16:05:26 +02:00
Clifford Wolf	7d2fb6e2fc	Fix smtbmc vlogtb bug in $anyseq handling	2017-07-01 02:13:32 +02:00
Clifford Wolf	0f217080cf	Add "design -import"	2017-06-30 19:18:52 +02:00
Clifford Wolf	8952bd6f45	Add chtype command	2017-06-30 17:57:34 +02:00
Clifford Wolf	18c030a8c9	Add $tribuf to opt_merge blacklist	2017-06-30 17:44:44 +02:00