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Code Activity
15377 commits 122 branches 59 tags 43 MiB
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534 commits

Author SHA1 Message Date
Miodrag Milanovic
8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic
9571acc0bf Support extended aiw format 2022-02-27 16:37:40 +01:00
Miodrag Milanovic
fca168797e Fix for last clock edge data 2022-02-25 16:15:32 +01:00
Claire Xenia Wolf
ca261d3c28 Experimental sim changes 2022-02-25 16:02:06 +01:00
Claire Xen
a41c1df76f
Merge pull request #3211 from YosysHQ/micko/witness 
Add support for AIGER witness files in "sim" command
 2022-02-22 16:22:06 +01:00
Miodrag Milanovic
fd3f08753a Fix handling of ce_over_srst 2022-02-21 16:36:12 +01:00
Claire Xenia Wolf
1aa9ad25d0 Fix cycle 0 in aiger witness co-simulation 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-02-18 16:27:41 +01:00
Miodrag Milanovic
41754b4207 Added AIGER witness file co simulation 2022-02-18 15:04:02 +01:00
Miodrag Milanovic
13a5c28459 simplify logic of handling flip-flops and latches 2022-02-18 09:17:36 +01:00
Miodrag Milanovic
61752b255f Review cleanup 2022-02-17 17:18:36 +01:00
Miodrag Milanovic
fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Claire Xen
49545c73f7
Merge branch 'master' into clk2ff-better-names 2022-02-11 16:03:12 +01:00
Miodrag Milanović
d7f7227ce8
Merge pull request #3185 from YosysHQ/micko/co_sim 
Add co-simulation in sim pass
 2022-02-07 16:36:43 +01:00
Miodrag Milanovic
c0a156bcb4 Error detection for co-simulation 2022-02-04 11:11:36 +01:00
Miodrag Milanovic
6db23de7b1 bug fix and cleanups 2022-02-04 10:01:06 +01:00
Miodrag Milanovic
990aee5531 respect hide_internal flag 2022-02-02 10:15:22 +01:00
Miodrag Milanovic
169ffcd2fb unify cycles counting and cleanup 2022-02-02 10:08:23 +01:00
Miodrag Milanovic
820b2fdd65 added stimulus mode and param check 2022-02-02 09:37:32 +01:00
Miodrag Milanovic
8ba2000a50 error when no signal found 2022-01-31 17:41:50 +01:00
Miodrag Milanovic
1b5ff92e62 Cleanup 2022-01-31 13:45:28 +01:00
Miodrag Milanovic
eabd0ff115 Compare bits when not all are defined 2022-01-31 13:41:02 +01:00
Miodrag Milanovic
26de52fa09 Cleanup 2022-01-31 12:00:15 +01:00
Miodrag Milanovic
6513300db7 message update 2022-01-31 11:41:52 +01:00
Miodrag Milanovic
543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic
a6959d30df Use edges when explicit 2022-01-31 09:38:25 +01:00
Miodrag Milanovic
cbadfa0268 Updating initial state and checks 2022-01-31 09:19:34 +01:00
Miodrag Milanovic
190e44f0da Fix scope 2022-01-31 08:56:29 +01:00
Marcelina Kościelnicka
93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Miodrag Milanovic
f04d1398e5 check if stop before start 2022-01-28 19:41:43 +01:00
Miodrag Milanovic
ecbba625c4 set initial state, only flip-flops 2022-01-28 15:59:13 +01:00
Miodrag Milanovic
cb12b7c4d8 ignore not found private signals 2022-01-28 14:20:16 +01:00
Miodrag Milanovic
81b76155d6 recursive check 2022-01-28 13:24:38 +01:00
Miodrag Milanovic
4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic
3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Miodrag Milanovic
40018e191b Display values of outputs 2022-01-26 16:52:36 +01:00
Miodrag Milanovic
be7be63fec Check if stimulated 2022-01-26 15:51:43 +01:00
Miodrag Milanovic
9a8939f0a4 Read fst and use data to set inputs 2022-01-26 15:50:38 +01:00
Miodrag Milanovic
ccfc00705a Add ability to write to FST file 2022-01-26 09:26:19 +01:00
Marcelina Kościelnicka
4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka
63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka
19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Claire Xenia Wolf
0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
 2021-06-09 12:16:56 +02:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
1c903d3e47 sim: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
 2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
c00a29296c sim: Avoid a crash on empty cell connection. 
Fixes #2513.
 2021-03-08 17:03:31 +01:00
Noah Moroze
90b40aa51f clk2fflogic: nice names for autogenerated signals 2021-03-02 18:28:56 -05:00
Marcelina Kościelnicka
4746ffd7b2 assertpmux: Fix crash on unused $pmux output. 
Fixes #2595.
 2021-02-22 23:30:28 +01:00
Gabriel Somlo
150b729b6f Add #include needed to build with gcc-11 
Suggested by Jeff Law <law@redhat.com>
 2020-11-26 06:12:12 -05:00
Chris Dailey
cdc802e4b7
Add rewrite_filename for sim -vcd argument. 2020-11-24 15:17:16 -05:00