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									 Clifford Wolf | 7d9a90396d | Added verilog frontend -ignore_redef option | 2013-11-24 19:57:42 +01:00 |  | 
				
					
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									 Clifford Wolf | f71e27dbf1 | Remove auto_wire framework (smarter than the verilog standard) | 2013-11-24 17:29:11 +01:00 |  | 
				
					
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									 Clifford Wolf | 609caa23b5 | Implemented correct handling of signed module parameters | 2013-11-24 17:17:21 +01:00 |  | 
				
					
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									 Clifford Wolf | 09471846c5 | Major improvements in mem2reg and added "init" sync rules | 2013-11-21 13:49:00 +01:00 |  | 
				
					
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									 Clifford Wolf | 943329c1dc | Various ast changes for early expression width detection (prep for constfold fixes) | 2013-11-02 13:00:17 +01:00 |  | 
				
					
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									 Clifford Wolf | 23cf23418c | Fixed handling of boolean attributes (frontends) | 2013-10-24 11:20:13 +02:00 |  | 
				
					
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									 Clifford Wolf | 4214561890 | Improved ast dumping (ast/verilog frontend) | 2013-08-19 19:49:14 +02:00 |  | 
				
					
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									 Clifford Wolf | 0f38008ed3 | Added "design" command (-reset, -save, -load) | 2013-07-27 14:27:51 +02:00 |  | 
				
					
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									 Clifford Wolf | 00a6c1d9a5 | Major redesign of expr width/sign detecion (verilog/ast frontend) | 2013-07-09 14:31:57 +02:00 |  | 
				
					
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									 Clifford Wolf | 56432a920f | Added defparam support to Verilog/AST frontend | 2013-07-04 14:12:33 +02:00 |  | 
				
					
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									 Clifford Wolf | db98a18edb | Enabled AST/Verilog front-end optimizations per default | 2013-06-10 13:19:04 +02:00 |  | 
				
					
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									 Clifford Wolf | f1a2fd966f | Now only use value from "initial" when no matching "always" block is found | 2013-03-31 11:51:12 +02:00 |  | 
				
					
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									 Clifford Wolf | 161565be10 | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) | 2013-03-31 11:19:11 +02:00 |  | 
				
					
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									 Clifford Wolf | 7bfc7b61a8 | Implemented proper handling of stub placeholder modules | 2013-03-28 09:20:10 +01:00 |  | 
				
					
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									 Clifford Wolf | 227520f94d | Added nosync attribute and some async reset related fixes | 2013-03-25 17:13:14 +01:00 |  | 
				
					
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									 Clifford Wolf | df9753d398 | Added mem2reg option to verilog frontend | 2013-03-24 11:13:32 +01:00 |  | 
				
					
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									 Clifford Wolf | bb3357c027 | Improved mem2reg handling in ast simplifier | 2013-03-24 09:27:01 +01:00 |  | 
				
					
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									 Clifford Wolf | 4f0c2862a0 | Added support for verilog genblock[index].member syntax | 2013-02-26 13:18:22 +01:00 |  | 
				
					
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									 Clifford Wolf | 7764d0ba1d | initial import | 2013-01-05 11:13:26 +01:00 |  |