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8439 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
8b47d16d7d Add testcase 2020-01-21 16:20:51 -08:00
Eddie Hung
dd3c3c0bdc read_verilog: simplify ternary condition early, ignore unreach children 2020-01-21 16:14:11 -08:00
Claire Wolf
5791c52e1b
Merge pull request #1637 from YosysHQ/mwk/fix-1634 
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
 2020-01-21 18:37:06 +01:00
Claire Wolf
30642e9570
Merge pull request #1629 from YosysHQ/mwk/edif-z 
edif: Just ignore connections to 'z
 2020-01-21 18:35:15 +01:00
Claire Wolf
f165a74824
Merge pull request #1621 from YosysHQ/clifford/fminit 
Add fminit pass
 2020-01-20 22:01:57 +01:00
Eddie Hung
b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map 
Cleanup +/xilinx/arith_map.v
 2020-01-18 09:11:52 -08:00
David Shah
a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning 
ice40: Demote conflicting FF init values to a warning
 2020-01-18 09:47:17 +00:00
Eddie Hung
67c6bf0b6b
Merge pull request #1645 from YosysHQ/eddie/fix1644 
{ice40,xilinx}_dsp: improve robustess
 2020-01-17 19:25:59 -08:00
Eddie Hung
6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63 Consistency 2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e xilinx_dsp: add parameter defaults 2020-01-17 16:05:10 -08:00
Eddie Hung
5507c328ff Add #1644 testcase 2020-01-17 15:57:52 -08:00
Eddie Hung
78ffd5d193 synth_ice40: call wreduce before mul2dsp 2020-01-17 15:41:55 -08:00
Eddie Hung
ad6c49fff1 ice40_dsp: add test 2020-01-17 15:38:26 -08:00
Eddie Hung
4985318263 ice40_dsp: add default values for parameters 2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558 ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs 2020-01-17 15:28:02 -08:00
Eddie Hung
5c589244df Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
Eddie Hung
1e6d56dca1 +/xilinx/arith_map.v fix $lcu rule 2020-01-17 11:28:37 -08:00
Eddie Hung
2bda51ac34
Merge pull request #1639 from YosysHQ/eddie/fix_read_xaiger 
read_aiger: $lut prefix in front
 2020-01-15 16:22:49 -08:00
Eddie Hung
5918ede9bd abc9: aAdd test to check $_NOT_s are absorbed 2020-01-15 14:36:05 -08:00
Eddie Hung
05c8858a90 read_aiger: $lut prefix in front 2020-01-15 14:31:32 -08:00
Miodrag Milanović
abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W 
synth_xilinx: fix default W value for non-xc7
 2020-01-15 08:47:16 +01:00
Eddie Hung
ffd6f54f92
Merge pull request #1635 from YosysHQ/eddie/print_stats 
print_stats footer to return peak memory, option for including children
 2020-01-14 14:18:42 -08:00
Marcin Kościelnicki
a5d2358a60 fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks. 
Fixes #1634.
 2020-01-14 22:49:20 +01:00
Eddie Hung
61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname 
autoname: do not rename ports
 2020-01-14 11:40:54 -08:00
Eddie Hung
9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630 
read_aiger: uniquify wires with $aiger<autoidx> prefix
 2020-01-14 11:40:40 -08:00
Eddie Hung
ade57058f7 As before, only display MEM if Linux or FreeBSD 2020-01-14 11:38:48 -08:00
Eddie Hung
36d1a2c60f synth_xilinx: fix default W value for non-xc7 2020-01-14 11:34:40 -08:00
Eddie Hung
a901a5fb44 print_stats footer to return peak memory, option for including children 2020-01-14 11:25:23 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung
de969adcd8 autoname: do not autoname ports 2020-01-14 10:13:29 -08:00
Eddie Hung
00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung
f63f76c372 read_aiger: also rename "$0" 2020-01-14 09:01:53 -08:00
Eddie Hung
ee95fa959a read_aiger: uniquify wires with $aiger<autoidx> prefix 2020-01-13 21:28:27 -08:00
Eddie Hung
565d349dc9 Add #1630 testcase 2020-01-13 21:27:53 -08:00
Eddie Hung
766e16b525 read_aiger: make $and/$not/$lut the prefix not suffix 2020-01-13 17:34:37 -08:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung
0f489c5ea3
Merge pull request #1627 from YosysHQ/eddie/fix1626 
synth_ice40: -abc2 to always use `abc` even if `-abc9`
 2020-01-13 08:17:34 -08:00
Marcin Kościelnicki
55f86eda36 edif: Just ignore connections to 'z 
Connecting a const 'z to a net should be equivalent to not connecting it
at all, so let's just ignore such connections on output.
 2020-01-13 14:49:31 +01:00
Eddie Hung
ae619ba87a Add #1626 testcase 2020-01-12 15:21:26 -08:00
Eddie Hung
c0b55deb0b synth_ice40: -abc2 to always use abc even if -abc9 2020-01-12 11:26:05 -08:00
Eddie Hung
35e49fde4d Another conflict 2020-01-11 18:57:25 -08:00
Eddie Hung
58ab9f6021 write_xaiger: create holes_sigmap before modifications 2020-01-11 17:25:32 -08:00
Eddie Hung
556ed0e18a MIssed this merge conflict 2020-01-11 17:05:30 -08:00
Eddie Hung
c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Eddie Hung
04a2eb8204
Merge pull request #1625 from YosysHQ/eddie/abc9_mfs 
abc9: re-enable "&mfs" optimisation for synth_{xilinx,ecp5}
 2020-01-11 13:49:24 -08:00
Eddie Hung
c820682314 abc9: fix help message, found by @nakengelhardt 2020-01-11 12:11:35 -08:00
Eddie Hung
1ccee4b95e write_xaiger: sort holes by offset as well as port_id 2020-01-11 11:49:57 -08:00
Eddie Hung
45d9caf3f9 abc9: remove -nomfs option 2020-01-11 08:08:35 -08:00