mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-17 18:06:41 +00:00
Code Activity
5126 commits 122 branches 56 tags 58 MiB
Commit graph

1 commit

Author SHA1 Message Date
tux3
88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00