Eddie Hung
c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
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kernel: share a single CellTypes within a pass
2020-04-01 14:17:45 -07:00
Eddie Hung
4ae7f3a8ed
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
2020-04-01 14:17:01 -07:00
Eddie Hung
e79bc45975
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
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opt_expr: improve performance on $alu and $sub
2020-04-01 14:11:09 -07:00
David Shah
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
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verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
Eddie Hung
d8dd842c09
Merge pull request #1852 from boqwxp/cleanup_synth_ice40
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Fix indentation in `techlibs/ice40/synth_ice40.cc`.
2020-04-01 11:18:38 -07:00
David Shah
c3997c77a5
verilog: Add location info for generate constructs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
Eddie Hung
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
Eddie Hung
86380e0212
Merge pull request #1849 from boqwxp/cleanup_kernel_yosys
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Clean up pseudo-private member usage in `kernel/yosys.cc`.
2020-04-01 09:35:35 -07:00
Eddie Hung
903cec84f4
Merge pull request #1850 from boqwxp/cleanup_backends
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Cleanup pseudo-private member usage and outdated `RTLIL::id2cstr()` in backends
2020-04-01 09:34:02 -07:00
Alberto Gonzalez
fc6b898178
Fix indentation in techlibs/ice40/synth_ice40.cc.
2020-04-01 16:29:56 +00:00
Alberto Gonzalez
c23c2c59c1
Update RTLIL::id2cstr() usage to log_id.
2020-04-01 06:53:28 +00:00
Claire Wolf
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
Alberto Gonzalez
cdb14652be
Clean up pseudo-private member usage in backends/intersynth/intersynth.cc.
2020-04-01 06:32:09 +00:00
Alberto Gonzalez
24ef73904f
Clean up pseudo-private member usage in backends/blif/blif.cc.
2020-04-01 05:50:48 +00:00
Alberto Gonzalez
f657fed24c
Clean up pseudo-private member usage in backends/verilog/verilog_backend.cc.
2020-04-01 05:25:10 +00:00
Alberto Gonzalez
68c0e3562e
Clean up pseudo-private member usage in backends/spice/spice.cc.
2020-04-01 04:56:52 +00:00
Alberto Gonzalez
057976c323
Clean up pseudo-private member usage in backends/edif/edif.cc.
2020-04-01 04:37:07 +00:00
Alberto Gonzalez
68fef4ca7f
Clean up pseudo-private member usage in backends/ilang/ilang_backend.cc.
2020-04-01 03:08:39 +00:00
Alberto Gonzalez
ae05795f54
Clean up pseudo-private member usage in kernel/yosys.cc.
2020-04-01 02:53:56 +00:00
Eddie Hung
1bb5a5215f
Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
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opt_merge: speedup
2020-03-31 14:50:32 -07:00
Eddie Hung
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
Eddie Hung
3df66027e0
Add dynamic slicing Verilog testcase
2020-03-31 11:51:31 -07:00
Diego H
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Diego H
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
Eddie Hung
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
Eddie Hung
3e88ede061
Merge pull request #1835 from boqwxp/cleanup_sat_expose
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Clean up pseudo-private member usage in `passes/sat/expose.cc`.
2020-03-30 13:05:12 -07:00
Eddie Hung
0d878ca256
Merge pull request #1832 from boqwxp/cleanup_passes_cmds_design
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Clean up pseudo-private member usage in `passes/cmds/design.cc`.
2020-03-30 11:56:17 -07:00
Eddie Hung
2c0739cbad
Merge pull request #1786 from boqwxp/hierarchycc_cleanup
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Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
2020-03-30 11:37:51 -07:00
Alberto Gonzalez
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to fixup_ports().
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
Eddie Hung
9f7d20a653
Merge pull request #1831 from boqwxp/cleanup_sat_eval
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Clean up pseudo-private member usage in `passes/sat/eval.cc`.
2020-03-30 11:13:53 -07:00
Eddie Hung
769c7318e7
Merge pull request #1833 from boqwxp/cleanup_sat_freduce
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Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
2020-03-30 11:13:06 -07:00
Alberto Gonzalez
00544cffab
Remove unused function parameter.
2020-03-30 18:00:19 +00:00
Alberto Gonzalez
5a0f029e23
Simplify iterating over selected modules or cells.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-30 17:56:07 +00:00
Alberto Gonzalez
7fc0938bb6
Replace RTLIL::id2cstr() with log_id().
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:50:36 +00:00
Alberto Gonzalez
4c92f9380c
Fix double deletion in passes/hierarchy/hierarchy.cc.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:43:54 +00:00
Alberto Gonzalez
f4faa1514b
Further clean up passes/sat/eval.cc.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:38:35 +00:00
Alberto Gonzalez
9f265dfd3f
Further clean up passes/sat/freduce.cc.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:25:30 +00:00
Alberto Gonzalez
696660351f
Clean up more in passes/sat/expose.cc.
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Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-30 16:16:16 +00:00
Eddie Hung
1d93d1e59f
memory_share: fix stray brace
2020-03-30 08:35:40 -07:00
Eddie Hung
4d897975a8
Code review fixes
2020-03-30 08:22:46 -07:00
Eddie Hung
f64d59d824
Apply suggestions from code review
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-03-30 08:19:56 -07:00
Marcin Kościelnicki
f68985f997
deminout: prevent any constant assignment from demoting to input
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Before this patch,
```
module top(inout io);
assign io = 1'bx;
endmodule
```
would have the `io` pin demoted to input (same happens for `1'bz`,
but not for `1'b0` or `1'b1`), resulting in check failures later on.
Part of fix for #1841 .
2020-03-30 15:04:31 +02:00
N. Engelhardt
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
N. Engelhardt
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
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Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
Miodrag Milanovic
1dbc701728
Explicit include of csignal
2020-03-28 09:49:08 +01:00
Miodrag Milanovic
5cdcd6ec79
windows - there are no stopping signals
2020-03-28 09:09:11 +01:00
Alberto Gonzalez
1197a43380
Clean up pseudo-private member usage in passes/sat/expose.cc.
2020-03-28 06:18:09 +00:00
Alberto Gonzalez
9a0cdc3835
Clean up pseudo-private member usage in passes/sat/freduce.cc.
2020-03-28 06:08:23 +00:00
Alberto Gonzalez
4681f02a6e
Clean up pseudo-private member usage in passes/cmds/design.cc.
2020-03-28 05:10:18 +00:00
Alberto Gonzalez
b63b2dbbc3
Clean up pseudo-private member usage in passes/sat/eval.cc.
2020-03-28 03:11:23 +00:00
