314 commits

Author	SHA1	Message	Date
Eddie Hung	85f1c2dcbe	Cleanup SRL inference/make more consistent	2019-06-29 21:42:20 -07:00
Eddie Hung	728839d6ca	Remove peepopt call in synth_xilinx since already in synth -run coarse	2019-06-28 12:53:38 -07:00
Eddie Hung	00f63d82ce	Reduce diff with upstream	2019-06-27 16:13:22 -07:00
Eddie Hung	9398921af1	Refactor for one "abc_carry" attribute on module	2019-06-27 16:07:14 -07:00
Eddie Hung	312c03e4ca	Remove redundant doc	2019-06-27 15:28:55 -07:00
Eddie Hung	1237a4c116	Add warning if synth_xilinx -abc9 with family != xc7	2019-06-27 11:22:49 -07:00
Eddie Hung	6c256b8cda	Merge origin/master	2019-06-27 11:20:15 -07:00
Eddie Hung	a7a88109f5	Update comment on boxes	2019-06-26 20:00:15 -07:00
Eddie Hung	b7bef15b16	Add "WE" to dist RAM's abc_scc_break	2019-06-26 19:58:09 -07:00
Eddie Hung	5e1b8d458b	Remove unused var	2019-06-26 10:33:07 -07:00
Eddie Hung	988e6163ab	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00
Eddie Hung	799b18263f	Merge branch 'koriakin/xc7nocarrymux' into xaig	2019-06-26 10:04:01 -07:00
Eddie Hung	7389b043c0	Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux	2019-06-26 09:33:38 -07:00
Eddie Hung	480a04cb3c	Realistic delays for RAM32X1D too	2019-06-25 09:34:28 -07:00
Eddie Hung	6095357390	Add RAM32X1D box info	2019-06-25 09:34:19 -07:00
Eddie Hung	6f36ec8ecf	Merge remote-tracking branch 'origin/master' into xaig	2019-06-25 09:33:11 -07:00
Eddie Hung	2f770b7400	Use LUT delays for dist RAM delays	2019-06-24 23:02:53 -07:00
Eddie Hung	152e682bd5	Add Xilinx dist RAM as comb boxes	2019-06-24 21:54:01 -07:00
Eddie Hung	efd04880db	Add RAM32X1D support	2019-06-24 16:16:50 -07:00
Eddie Hung	792d0670c3	Add comment to xc7 box	2019-06-22 14:28:24 -07:00
Eddie Hung	7903ebe3e0	Carry in/out box ordering now move to end, not swap with end	2019-06-22 14:18:42 -07:00
Eddie Hung	65c022c257	Remove DFF and RAMD box info for now	2019-06-21 20:41:14 -07:00
Eddie Hung	f11c9a419b	Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc	2019-06-20 17:38:16 -07:00
Eddie Hung	8e0a47fb92	Really permute Xilinx LUT mappings as default LUT6.I5:A6	2019-06-18 11:48:48 -07:00
Eddie Hung	8f5e6d73ff	Revert "Fix (do not) permute LUT inputs, but permute mux selects" ... This reverts commit da3d2eedd2.	2019-06-18 11:35:21 -07:00
Eddie Hung	da3d2eedd2	Fix (do not) permute LUT inputs, but permute mux selects	2019-06-18 09:49:57 -07:00
Eddie Hung	608a95eb01	Fix copy-pasta issue	2019-06-17 22:29:22 -07:00
Eddie Hung	2a35c4ef94	Permute INIT for +/xilinx/lut_map.v	2019-06-17 22:24:35 -07:00
Eddie Hung	75f8b4cf10	Simplify comment	2019-06-17 19:14:41 -07:00
Eddie Hung	840562943f	Update LUT7/8 delays to take account for [ABC]OUTMUX delay	2019-06-17 17:06:01 -07:00
Eddie Hung	c15ee827f4	Try -W 300	2019-06-17 10:29:06 -07:00
Eddie Hung	bf312043d4	Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O	2019-06-15 05:45:16 -07:00
Eddie Hung	8fa74287a7	As per @daveshah1 remove async DFF timing from xilinx	2019-06-14 12:43:20 -07:00
Eddie Hung	2e34859a6b	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	2019-06-14 11:38:22 -07:00
Eddie Hung	ba4b4a0088	Update delays based on SymbiFlow/prjxray-db	2019-06-14 11:33:10 -07:00
Eddie Hung	d47ff7ba87	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	2019-06-14 10:51:11 -07:00
Eddie Hung	ee428f73ab	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00
Eddie Hung	627a62a797	Make doc consistent	2019-06-14 10:32:46 -07:00
Eddie Hung	75d89e56cf	Fix name clash	2019-06-13 14:27:07 -07:00
Eddie Hung	009255d11d	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	2019-06-12 16:07:24 -07:00
Eddie Hung	c7f5091c2f	Reduce diff with master	2019-06-12 09:34:41 -07:00
Eddie Hung	99267f660f	Fix spacing	2019-06-12 09:21:52 -07:00
Eddie Hung	738fdfe8f5	Remove wide mux inference	2019-06-12 09:20:46 -07:00
Eddie Hung	1e838a8913	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	2019-06-12 08:49:15 -07:00
Eddie Hung	4c9fde87d1	Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" ... This reverts commit 2dffa4685b.	2019-06-12 08:48:45 -07:00
Eddie Hung	2dffa4685b	Add "-W' wire delay arg to abc9, use from synth_xilinx	2019-06-11 17:10:47 -07:00
Eddie Hung	54379f9872	Disable dist RAM boxes due to comb loop	2019-06-11 12:02:51 -07:00
Eddie Hung	8a708d1fdb	Remove #ifndef ABC	2019-06-11 12:02:31 -07:00
Eddie Hung	b77c5da769	Revert "Revert "Move ff_map back after ABC for shregmap"" ... This reverts commit e473e74565.	2019-06-10 14:37:09 -07:00
Eddie Hung	a1d4ae78a0	Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" ... This reverts commit 94a5f4e609.	2019-06-10 14:34:43 -07:00