Eddie Hung 1e838a8913 Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"		2019-06-12 08:49:15 -07:00
..
tests
.gitignore
abc.box	Add flops as blackboxes	2019-05-31 18:11:46 -07:00
abc.lut	Some more realistic delays...	2019-05-29 22:55:34 -07:00
arith_map.v	Instead of MUXCY/XORCY use CARRY4 (with timing)	2019-05-21 16:19:45 -07:00
brams.txt
brams_bb.v	Add (* abc_flop_q *) to brams_bb.v	2019-06-04 11:53:51 -07:00
brams_init.py
brams_map.v
cells_map.v	$__XILINX_MUX_ -> $__XILINX_SHIFTX	2019-06-06 15:32:36 -07:00
cells_sim.v	Disable dist RAM boxes due to comb loop	2019-06-11 12:02:51 -07:00
cells_xtra.sh	Typo	2019-05-28 09:36:01 -07:00
cells_xtra.v	Add whitebox support to DRAM	2019-05-23 08:58:57 -07:00
drams.txt	Add "min bits" and "min wports" to xilinx dram rules	2019-05-23 11:32:28 -07:00
drams_map.v
ff_map.v	Cleanup	2019-06-05 12:28:46 -07:00
lut_map.v
Makefile.inc	Add mux_map.v for wide mux	2019-06-04 09:51:47 -07:00
mux_map.v	$__XILINX_MUX_ -> $__XILINX_SHIFTX	2019-06-06 15:32:36 -07:00
synth_xilinx.cc	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	2019-06-12 08:49:15 -07:00