Emil J. Tywoniak
8582136a45
simplify: fix $initstate segfault
2025-08-12 12:39:36 +02:00
Emil J
fb024c4d55
Merge pull request #5135 from YosysHQ/emil/ast-ownership
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ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-08-12 10:58:12 +02:00
KrystalDelusion
407d425114
Merge pull request #5024 from YosysHQ/krys/update_evals
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Updating test_cell
2025-08-12 14:27:03 +12:00
Krystine Sherwin
1e6e25c81f
ci: Use correct build artifact
2025-08-12 12:43:14 +12:00
Krystine Sherwin
c630f995d5
ci: Reduce test_cell count and use a seed
2025-08-12 11:17:00 +12:00
Krystine Sherwin
ba01f7c64f
ci: Run test_cell
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Includes special cases for partially supported cells.
2025-08-12 10:57:59 +12:00
Krystine Sherwin
1afe8d9f4d
celltypes: Comment pointing to ConstEval
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`CellTypes::eval()` is more generic but also more limited. `ConstEval::eval()` requires more setup (both in code and at runtime) but has more complete support.
2025-08-12 10:57:59 +12:00
Krystine Sherwin
20c2d2a6f3
test_cell: Add comment on $pmux
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`-simlib` also doesn't work.
2025-08-12 10:57:59 +12:00
Martin Povišer
c589714433
test_cell: Update to $macc_v2
2025-08-12 10:57:59 +12:00
Krystine Sherwin
db4ffaffd2
consteval: Fix $bwmux handling
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If the cell type has a S signal and hasn't already been handled, use `CellTypes::eval(cell, A, B, S)`.
2025-08-12 10:57:58 +12:00
Krystine Sherwin
014eadd8b9
test_cell: Fix $bweqx
2025-08-12 10:57:58 +12:00
Krystine Sherwin
22aa9fba3b
test_cell: Support more cell types
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Still unsupported:
- wide muxes (`$_MUX16_` and friends)
Partially supported types have comments in `test_cell.cc`.
Fix `CellTypes::eval() for `$_NMUX_`.
Fix `RTLIL::Cell::fixup_parameters()` for $concat, $bwmux and $bweqx.
2025-08-12 10:57:58 +12:00
Krystine Sherwin
481ecb51a7
test_cell: Disable $macc testing
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Needs updating to `$macc_v2`.
2025-08-12 10:57:58 +12:00
Jannis Harder
2d90e80b52
Merge pull request #5270 from zhanghongce/main
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Reorder the port wire declarations to follow the same order of the port declarations
2025-08-11 15:35:25 +02:00
Emil J. Tywoniak
642e041f77
const2ast: fix for consistency with previous diagnostics behavior
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
99ab73424d
verilog_location: rename location to Location to avoid conflict with Pass::location
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5195f81257
ast: fix import node
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
df8422d244
verilog_lexer: refactor
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
740ed3fc1c
ast: refactor
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
646c45e6b8
ast: remove null_check as dead code
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
25d2a8ce3a
simplify: simplify
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
97bc0088d8
simplify: std::gcd
2025-08-11 13:34:10 +02:00
Krystine Sherwin
d3e33a3be5
simplify.cc: Drop unused debug prints
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At least the ones added by this PR. There are some unused debug prints that are *changed* by this PR, but I've left them.
2025-08-11 13:34:10 +02:00
Krystine Sherwin
9b882c32c1
frontends/ast: More usage of auto
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For consistency.
2025-08-11 13:34:10 +02:00
Krystine Sherwin
720f33271d
docs: Update ubuntu apt-get
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Also mention CXXSTD fix for cygwin.
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5b62616b63
preproc: formatting
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
9a10f4c02f
verilog_lexer, verilog_parser: remove comment
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
ae65b4fc84
verilog_lexer: fix fallthrough warning
2025-08-11 13:34:10 +02:00
Emil J
39c5c256c0
verilog_lexer: remove comment
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
abb8b8d28b
preproc: formatting
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
deedfbefe2
fixup! readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
cbccc01d38
Revert "CI: bump flex and bison on Windows"
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This reverts commit efbc138ced
2025-08-11 13:34:10 +02:00
Emil J
aedc237c7a
rtlil: remove comment
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-08-11 13:34:10 +02:00
Krystine Sherwin
1a63dd56bd
Add flex lib to vcxsrc include dirs
2025-08-11 13:34:10 +02:00
Krystine Sherwin
4f824e4223
Sneak FlexLexer.h into VS build
2025-08-11 13:34:10 +02:00
Catherine
8455503a50
CI: fix typo
2025-08-11 13:34:10 +02:00
Catherine
4956d3cce5
CI: install flex for WASI builds.
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
0ce51029f6
fixup! CI: sneak FlexLexer.h into the WASI sysroot
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
3ec3afb414
CI: bump flex and bison on Windows
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
f3ebf0557e
CI: sneak FlexLexer.h into the WASI sysroot
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
85b5a7d08b
verilog: fix build dependency graph
2025-08-11 13:34:10 +02:00
Gary Wong
4ffd05af6f
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-08-11 13:34:10 +02:00
garytwong
105a3cd32d
verilog: fix string literal regular expression ( #5187 )
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* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
0a5aa4c78b
docs: fix verilog frontend internals
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
42b5c14e35
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
e6e680cd62
readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-08-11 13:34:10 +02:00
Krystine Sherwin
0f7080ebf8
dpicall.cc: Fix sans-plugin function call
2025-08-11 13:34:10 +02:00
Krystine Sherwin
f4016d96cc
Makefile: Add flex lib/include for brew
2025-08-11 13:34:10 +02:00
Krystine Sherwin
d2573f168d
preproc.cc: Use full path for generated file
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Fixes out-of-tree builds.
2025-08-11 13:34:10 +02:00
Krystine Sherwin
69f2f3ca81
docs/verilog_frontend.rst: Fix indentation
2025-08-11 13:34:10 +02:00
