Jannis Harder
ce708122a5
New xprop pass to encode 3-valued x-propagation using 2-valued logic
2022-11-30 19:01:28 +01:00
Jannis Harder
5ff69a0fe2
sim: Improved global clock handling
2022-11-30 18:50:53 +01:00
Jannis Harder
3ecf85e32c
opt_expr: Optimizations for $bweqx and $bwmux
2022-11-30 18:50:53 +01:00
Jannis Harder
be752a20dc
Add bwmuxmap pass
2022-11-30 18:50:53 +01:00
Jannis Harder
7203ba7bc1
Add bitwise $bweqx and $bwmux cells
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The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
Jannis Harder
f2c531e65f
verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode.
2022-11-30 18:24:35 +01:00
Jannis Harder
82b630a246
verilog_backend: Correctly sign extend output of signed $modfloor
2022-11-30 18:24:35 +01:00
Jannis Harder
5cb7d0fe9d
verilog_backend: Add -noparallelcase option
2022-11-30 18:24:35 +01:00
Jannis Harder
99163fb822
simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal
2022-11-30 18:24:35 +01:00
Jannis Harder
605d127517
simlib: Silence iverilog warning for $lut
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iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
2022-11-30 18:24:35 +01:00
Jannis Harder
39ac113402
simlib: Fix wide $bmux and avoid iverilog warnings
2022-11-30 18:24:35 +01:00
Jannis Harder
b982ab4f59
satgen, simlib: Consistent x-propagation for $pmux cells
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This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
2022-11-30 18:24:35 +01:00
Jannis Harder
1e67c3a3c2
opt_expr: Fix shift/shiftx optimizations
2022-11-30 18:24:25 +01:00
Miodrag Milanovic
2dd55d73a0
reset elaboration error after rewriter
2022-11-30 17:26:48 +01:00
Miodrag Milanovic
bfd79845b6
Set all verific messages of certain type to other
2022-11-30 16:42:37 +01:00
Miodrag Milanovic
b0469b3863
Fix tcl crash in case of error executing command
2022-11-30 15:54:31 +01:00
Jannis Harder
fd56d1f79e
opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells
2022-11-29 19:06:45 +01:00
Jannis Harder
c08242ba41
opt_expr: Optimize bitwise logic ops with one fully const input
2022-11-29 19:06:45 +01:00
Jannis Harder
661fa5ff92
simplemap: Map $xnor to $_XNOR_ cells
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The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
2022-11-29 19:06:45 +01:00
github-actions[bot]
f9db7c0599
Bump version
2022-11-29 00:18:02 +00:00
Jannis Harder
10e22608c0
Merge pull request #3565 from jix/sat-def-formal
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sat: Add -set-def-formal option to force defined $any* outputs
2022-11-28 16:04:38 +01:00
Jannis Harder
ed0e14820e
sat: Add -set-def-formal option to force defined $any* outputs
2022-11-28 14:50:52 +01:00
github-actions[bot]
23e26ff661
Bump version
2022-11-26 00:16:21 +00:00
Miodrag Milanović
fd01d9eb8b
Merge pull request #3561 from YosysHQ/tcl_shell
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Add TCL interactive shell mode
2022-11-25 18:12:43 +01:00
Miodrag Milanović
448a796e15
Merge pull request #3560 from YosysHQ/verific_conf
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Support importing verilog configurations using Verific
2022-11-25 17:40:57 +01:00
Miodrag Milanovic
2450e6be22
Add TCL interactive shell mode
2022-11-25 16:18:02 +01:00
Miodrag Milanovic
f764cd1655
update documentation
2022-11-25 14:27:30 +01:00
Miodrag Milanovic
b0be19c126
Support importing verilog configurations using Verific
2022-11-25 13:02:11 +01:00
github-actions[bot]
c55c514cdb
Bump version
2022-11-25 00:16:25 +00:00
KrystalDelusion
b9b5899cce
Remove docs dependency on yosys repo ( #3558 )
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* Copies guidelines files into docs/ for website
* Copying manual/CHAPTER_Prog for new docs
* Copying manual/APPNOTE_011... for new docs
Also adding faketime to list of packages for website build.
Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>
2022-11-24 15:56:44 +01:00
Dag Lem
a460e0b31c
Tests for unpacked arrays in packed structs are for the Yosys frontend only
2022-11-23 16:37:51 +01:00
Dag Lem
ddb12148e7
Support for swapped ranges in second array dimension
2022-11-23 16:31:08 +01:00
Jannis Harder
fc2f622a27
Merge pull request #3552 from daglem/fix-sv-c-array-dimensions
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Correct interpretation of SystemVerilog C-style array dimensions
2022-11-23 15:12:17 +01:00
github-actions[bot]
13e4f343b9
Bump version
2022-11-22 00:18:29 +00:00
Jannis Harder
239ecf9185
Merge branch 'zachjs-master'
2022-11-21 17:47:43 +01:00
N. Engelhardt
b64141f48b
mention prerequisites in fsm_detect and fsm help
2022-11-21 16:07:23 +01:00
github-actions[bot]
e56c689962
Bump version
2022-11-18 00:20:31 +00:00
gatecat
b6467f0801
fabulous: Allow adding extra custom prims and map rules
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-17 13:34:58 +01:00
gatecat
f111bbdf40
fabulous: improvements to the pass
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-17 13:34:58 +01:00
gatecat
e3f9ff2679
fabulous: Unify and update primitives
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Signed-off-by: gatecat <gatecat@ds0.me>
2022-11-17 13:34:58 +01:00
TaoBi22
12c22045b7
Introduce RegFile mappings
2022-11-17 13:34:58 +01:00
TaoBi22
2b07e01ea4
Replace synth call with components, reintroduce flags and correct vpr flag implementation
2022-11-17 13:34:58 +01:00
TaoBi22
df56178567
Reorder operations to load in primitive library before hierarchy pass
2022-11-17 13:34:58 +01:00
TaoBi22
da32f21b59
Add plib flag to specify custom primitive library path
2022-11-17 13:34:58 +01:00
TaoBi22
950dde3081
Remove flattening from FABulous pass
2022-11-17 13:34:58 +01:00
TaoBi22
8fdf4948a8
Remove ALL currently unused flags (some to be reintroduced later and passed through to synth)
2022-11-17 13:34:58 +01:00
TaoBi22
2e9480be24
Add synth_fabulous ScriptPass
2022-11-17 13:34:58 +01:00
github-actions[bot]
0516fd751c
Bump version
2022-11-17 00:19:18 +00:00
Miodrag Milanovic
48659ee2bb
Slowing down clock to have same metadata
2022-11-16 10:11:05 +01:00
github-actions[bot]
388611aac4
Bump version
2022-11-16 00:19:25 +00:00
