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Code Activity
5971 commits 98 branches 53 tags 41 MiB
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610 commits

Author SHA1 Message Date
Eddie Hung 812469aaa3 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 14:48:35 -07:00
Eddie Hung b2b5cf78e2 Rework muxcover decoder gen if more significant muxes are 1'bx 2019-06-26 13:50:19 -07:00
Eddie Hung 5b89553a1f nullptr check 2019-06-24 23:37:01 -07:00
Eddie Hung 1564eb8b54 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-24 22:48:49 -07:00
Eddie Hung a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung 5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung 49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung 6c2cb51996 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-21 17:44:21 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Eddie Hung cf4ac332e1 Do not rename non LUT cells in abc9 2019-06-21 15:46:45 -07:00
Eddie Hung 9edde91c26 Merge remote-tracking branch 'origin/clifford/fix1091' into xc7mux_wip 2019-06-21 10:51:41 -07:00
Clifford Wolf ec979475e7 Replace "muxcover -freedecode" with "muxcover -dmux=cost" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 19:24:41 +02:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Clifford Wolf 9286b6f013 Add "muxcover -freedecode" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 10:02:10 +02:00
Eddie Hung 54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00
Eddie Hung 06bf2ea562 Fix gcc warning of potentially uninitialised 2019-06-20 21:53:27 -07:00
Clifford Wolf 891ea6512e Improvements in muxcover 
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
 2019-06-20 19:47:59 -07:00
Clifford Wolf 40188457d1 Add support for partial matches to muxcover, fixes #1091 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 19:47:59 -07:00
Eddie Hung 0e97e6a00d Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:41:27 -07:00
Eddie Hung 242b72d4e1 Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:37:03 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung 9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Eddie Hung f54edf1e78 Do not call "setundef -zero" in abc9 2019-06-20 10:22:14 -07:00
Eddie Hung f374e0ab7e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-20 10:18:01 -07:00
Clifford Wolf 06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Eddie Hung 96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Eddie Hung 7324a4c2cd Remove iterator based Module::remove as per @cliffordwolf 2019-06-18 12:47:12 -07:00
Eddie Hung 4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung 63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung 7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Eddie Hung fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung 2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung a632799d5b Update abc9 -D doc 2019-06-14 12:29:46 -07:00
Eddie Hung e391fc8e7b Enable "abc9 -D <num>" for timing-driven synthesis 2019-06-14 12:28:01 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung 751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung a5425a2f7e Remove extra semicolon 2019-06-14 10:11:34 -07:00
David Shah 9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Eddie Hung 2c40b66785 Rip out all non FPGA stuff from abc9 2019-06-12 16:53:12 -07:00
Eddie Hung f81a189fb8 Fix spelling 2019-06-12 16:52:09 -07:00
Eddie Hung b3faf0246d Be more precise when connecting during ABC9 re-integration 2019-06-12 16:04:33 -07:00
Eddie Hung 2e7e73f483 Remove hacky wideports_split from abc9 2019-06-12 15:52:49 -07:00
Eddie Hung d9974b85e7 Fix compile errors when #if 1 for debug 2019-06-12 15:47:39 -07:00
Eddie Hung 8bb67fa67c Do not call abc9 if no outputs 2019-06-12 10:18:44 -07:00