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Fix simple_abc9/generate test with 1'bx at MSB

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This commit is contained in:
Eddie Hung 2019-06-20 19:37:03 -07:00
parent 494610911a
commit 242b72d4e1
1 changed files with 1 additions and 1 deletions
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2
passes/techmap/abc9.cc
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@ -492,7 +492,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (w->port_output) {
RTLIL::Wire *wire = module->wire(w->name);
log_assert(wire);
for (int i = 0; i < GetSize(wire); i++)
for (int i = 0; i < GetSize(w); i++)
output_bits.insert({wire, i});
}
}