Miodrag Milanovic
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80ba43d262
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Release version 0.44
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2024-08-06 09:42:28 +02:00 |
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Miodrag Milanović
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e5d8505349
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Merge pull request #4523 from YosysHQ/emil/no-lto-lld
Makefile: no LTO and lld by default
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2024-08-06 09:08:09 +02:00 |
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github-actions[bot]
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d2b5788674
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Bump version
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2024-08-06 00:18:14 +00:00 |
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Emil J. Tywoniak
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eeecb54532
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Makefile: no LTO and lld by default
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2024-08-05 19:28:09 +02:00 |
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N. Engelhardt
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01b99972b4
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Merge pull request #4518 from YosysHQ/micko/sim_signal_names
Set ranges on exported wires in VCD and FST
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2024-08-05 15:03:59 +02:00 |
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Miodrag Milanovic
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6d98418f3d
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Set ranges on exported wires in VCD and FST
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2024-08-02 15:23:00 +02:00 |
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github-actions[bot]
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c788484679
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Bump version
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2024-07-30 00:18:19 +00:00 |
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Miodrag Milanović
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3e14e67374
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Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase
VHDL is case insensitive, make sure netlist name is proper
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2024-07-29 16:44:13 +02:00 |
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Emil J
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92cac63845
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Merge pull request #4344 from widlarizer/emil/keep_hierarchy
cost: add keep_hierarchy pass with min_cost argument
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2024-07-29 16:33:08 +02:00 |
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Miodrag Milanovic
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405897a971
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Update top value that is returned back to hierarchy pass
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2024-07-29 15:50:38 +02:00 |
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N. Engelhardt
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9f869b265c
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Merge pull request #4474 from tony-min-1/mchp
Add PolarFire FPGA support
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2024-07-29 15:28:44 +02:00 |
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N. Engelhardt
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7c3666ff68
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Merge pull request #4505 from YosysHQ/micko/ext_register
Initialize extensions when Verific pass is registered
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2024-07-29 15:23:31 +02:00 |
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Emil J
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e21dd292fc
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Merge pull request #4502 from YosysHQ/emil/build-opt-levels
Release build configuration improvements
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2024-07-29 15:13:52 +02:00 |
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Emil J. Tywoniak
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af0c2fa659
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Brewfile: add llvm for lld
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2024-07-29 15:13:24 +02:00 |
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Emil J
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051d83205d
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Merge pull request #4471 from georgerennie/hashlib_primes
hashlib: Add some more primes
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2024-07-29 15:10:22 +02:00 |
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Martin Povišer
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61ae9f4e07
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Merge pull request #4514 from YosysHQ/emil/proc_rom-src-test-2
proc_rom: test src attribute on memories
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2024-07-29 13:58:19 +02:00 |
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Emil J. Tywoniak
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4b29f64142
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cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
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2024-07-29 10:26:02 +02:00 |
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Emil J
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49eaa108a5
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Merge pull request #4425 from YosysHQ/emil/doc-sigmap
sigmap: comments
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2024-07-29 10:18:44 +02:00 |
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Emil J. Tywoniak
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01fd72520f
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proc_rom: test src attribute on memories
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2024-07-29 10:13:45 +02:00 |
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github-actions[bot]
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960bca0196
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Bump version
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2024-07-27 00:17:35 +00:00 |
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Martin Povišer
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ced1313193
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Merge pull request #4510 from JamesTimothyMeech/patch-1
Update interactive_investigation.rst
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2024-07-26 15:17:57 +02:00 |
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James Meech
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1c41db6978
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Update interactive_investigation.rst
The text starting at line 118 refers to proc twice but it should refer to opt and then to proc.
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2024-07-26 13:53:08 +01:00 |
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N. Engelhardt
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dd3637f9f0
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Merge pull request #4506 from povik/synthprop-formatting
synthprop: Reformat the help
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2024-07-26 12:28:09 +02:00 |
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N. Engelhardt
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41b51c1ca9
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Merge pull request #4503 from RCoeurjoly/vhdl_extension
Guess VHDL frontend for both *.vhd and *vhdl files
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2024-07-26 10:44:10 +02:00 |
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github-actions[bot]
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610d27dc1c
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Bump version
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2024-07-26 00:17:42 +00:00 |
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Martin Povišer
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7ee685a0b0
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proc_rom: Set src on the emitted memory
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2024-07-25 23:14:27 +01:00 |
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Martin Povišer
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e063b96104
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synthprop: Reformat the help
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2024-07-25 11:43:58 +02:00 |
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Miodrag Milanovic
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9566709426
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Initialize extensions when verific pass is registered
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2024-07-25 11:25:17 +02:00 |
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Emil J. Tywoniak
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7cd27e1182
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Makefile: remove accidental abc opt level override for wasi builds
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2024-07-24 21:31:35 +02:00 |
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Emil J. Tywoniak
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29d53bc94a
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actions: try fix GITHUB_PATH
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2024-07-24 19:50:34 +02:00 |
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Emil J. Tywoniak
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ad47844bbf
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actions: macos install lld from llvm package
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2024-07-24 18:32:04 +02:00 |
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Roland Coeurjoly
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ce11ddbf21
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Simplified run_frontend by using a lambda function for file extension checks and combining blif and eblif into a single condition.
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2024-07-23 17:55:04 +02:00 |
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Roland Coeurjoly
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8c1431f373
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Guess VHDL frontend for both *.vhd and *vhdl files
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2024-07-23 17:01:57 +02:00 |
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Roland Coeurjoly
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5d0558932e
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Add llvmPackages.bintools to buildInputs, otherwise we get a linkage error
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2024-07-22 20:11:08 +02:00 |
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Emil J. Tywoniak
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a947572f38
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Add lld to clang build environments and Dockerfile
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2024-07-22 21:33:46 +02:00 |
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Emil J. Tywoniak
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bf758b9097
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Makefile: turn off LTO on gcc due to regression
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2024-07-22 20:59:56 +02:00 |
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Martin Povišer
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118b2829db
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Merge pull request #4499 from YosysHQ/emil/ast-comments
ast: don't suggest use in external projects
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2024-07-19 10:33:50 +02:00 |
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github-actions[bot]
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28ebefda4a
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Bump version
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2024-07-19 00:17:55 +00:00 |
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Miodrag Milanovic
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c94aa719d9
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VHDL is case insensitive, make sure netlist name is proper
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2024-07-18 16:56:52 +02:00 |
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Emil J. Tywoniak
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72a0380da8
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ast: don't suggest use in external projects
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2024-07-18 16:37:14 +02:00 |
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Emil J. Tywoniak
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583db7b15e
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sigmap: comments
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2024-07-18 16:02:11 +02:00 |
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Martin Povišer
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81df8557d9
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Merge pull request #4494 from povik/install-bitpattern-h
Makefile: do install `bitpattern.h`
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2024-07-18 15:50:58 +02:00 |
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Emil J
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43c1328fbb
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Merge pull request #4479 from yrabbit/z1-power
Gowin. Add an energy saving primitive
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2024-07-18 11:56:00 +02:00 |
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Emil J
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1440f624ee
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Merge pull request #4489 from yrabbit/dcs
Gowin. Add the DCS primitive
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2024-07-18 11:55:38 +02:00 |
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Emil J
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1d7a47bb6b
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Merge pull request #4487 from YosysHQ/emil/abc-reproducible-git-hash
Reproducible git hash
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2024-07-18 11:54:07 +02:00 |
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Martin Povišer
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ec32c9a056
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Makefile: do install bitpattern.h
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2024-07-17 18:26:12 +02:00 |
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github-actions[bot]
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49f547782c
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Bump version
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2024-07-16 00:18:08 +00:00 |
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Emil J
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1166238c0f
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Merge pull request #4176 from povik/opt_expr-performance
Improve `opt_expr` performance
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2024-07-15 16:10:25 +02:00 |
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Emil J
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9abdf363a3
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Merge pull request #4428 from kallisti5/haikuisms
haiku: Basic fixes to build under Haiku
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2024-07-15 13:32:24 +02:00 |
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Alexander von Gluck
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2f514487cb
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haiku: Basic fixes to build under Haiku
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2024-07-15 12:57:34 +02:00 |
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