3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-23 16:04:37 +00:00
Commit graph

1 commit

Author SHA1 Message Date
Krystine Sherwin
805f110aef analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
2025-10-18 12:14:03 +01:00