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https://github.com/YosysHQ/yosys
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analogdevices: Extra tests
`mem_gen.py` based on quicklogic tests. Remove BUFG from `lutram.ys`. Extra `sync_ram_sp` models in `arch/common/blockram.v`. Add analogdevices to main makefile tests. Not all the other tests are passing, but that's fine for now.
This commit is contained in:
Krystine Sherwin
Lofty
parent
f2b88c23d4
commit
805f110aef
6 changed files with 211 additions and 13 deletions
1
Makefile
1
Makefile
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@ -879,6 +879,7 @@ endif
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# Tests that generate .mk with tests/gen-tests-makefile.sh
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MK_TEST_DIRS =
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MK_TEST_DIRS += tests/arch/analogdevices
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MK_TEST_DIRS += tests/arch/anlogic
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MK_TEST_DIRS += tests/arch/ecp5
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MK_TEST_DIRS += tests/arch/efinix
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1
tests/arch/analogdevices/.gitignore
vendored
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1
tests/arch/analogdevices/.gitignore
vendored
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@ -0,0 +1 @@
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t_*.ys
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@ -12,10 +12,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FFRE
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select -assert-count 8 t:RAMS32X1
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select -assert-none t:BUFG t:FFRE t:RAMS32X1 %% t:* %D
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select -assert-none t:FFRE t:RAMS32X1 %% t:* %D
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design -reset
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@ -33,10 +32,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w1r
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dump
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FFRE
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select -assert-count 8 t:RAMS64X1
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select -assert-none t:BUFG t:FFRE t:RAMS64X1 %% t:* %D
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select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
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design -reset
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@ -53,10 +51,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w3r
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select -assert-count 1 t:BUFG
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select -assert-count 24 t:FFRE
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select -assert-count 16 t:RAMD32X1
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select -assert-none t:BUFG t:FFRE t:RAMD32X1 %% t:* %D
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select -assert-none t:FFRE t:RAMD32X1 %% t:* %D
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design -reset
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@ -73,10 +70,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w3r
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select -assert-count 1 t:BUFG
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select -assert-count 24 t:FFRE
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select -assert-count 16 t:RAMD64X1
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select -assert-none t:BUFG t:FFRE t:RAMD64X1 %% t:* %D
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select -assert-none t:FFRE t:RAMD64X1 %% t:* %D
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design -reset
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@ -93,10 +89,9 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 6 t:FFRE
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select -assert-count 6 t:RAMS32X1
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select -assert-none t:BUFG t:FFRE t:RAMS32X1 %% t:* %D
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select -assert-none t:FFRE t:RAMS32X1 %% t:* %D
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design -reset
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@ -113,7 +108,6 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 6 t:FFRE
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select -assert-count 6 t:RAMS64X1
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select -assert-none t:BUFG t:FFRE t:RAMS64X1 %% t:* %D
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select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
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121
tests/arch/analogdevices/mem_gen.py
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121
tests/arch/analogdevices/mem_gen.py
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@ -0,0 +1,121 @@
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from __future__ import annotations
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from dataclasses import dataclass
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blockram_template = """# ======================================
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log ** GENERATING TEST {top} WITH PARAMS{param_str}
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design -reset; read_verilog -defer ../common/blockram.v
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chparam{param_str} {top}
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hierarchy -top {top}
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echo on
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debug synth_analogdevices -tech {tech} -top {top} {opts} -run :map_ffram
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stat; echo off
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"""
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inference_tests: "list[tuple[str, list[tuple[str, int]], str, list[str], list[str]]]" = [
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# RBRAM2 has TDP and SDP for 8192x5bit, 4096x9bit, and 2048x40bit
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("t16ffc", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 5)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t16ffc", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 40)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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# LUTRAM is generally cheaper than BRAM for undersized (SDP) memories
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("t16ffc", [("ADDRESS_WIDTH", 6), ("DATA_WIDTH", 1)], "sync_ram_sdp", ["-assert-count 1 t:RAMD64X1"], []),
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("t16ffc", [("ADDRESS_WIDTH", 6), ("DATA_WIDTH", 8)], "sync_ram_sdp", ["-assert-count 8 t:RAMD64X1"], []),
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("t16ffc", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 8)], "sync_ram_sdp", ["-assert-count 128 t:RAMD64X1"], []),
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("t16ffc", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 16)], "sync_ram_sdp", ["-assert-count 256 t:RAMD64X1"], []),
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# RBRAM is half the depth of RBRAM2, and doesn't have TDP, also LUTRAM is cheaper, so we need to specify not to use it
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("t40lp", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 5)], "sync_ram_sdp", ["-assert-count 2 t:RBRAM"], ["-nolutram"]),
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("t40lp", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 5)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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("t40lp", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 40)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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# 2048x32 and 2048x36bit are also valid
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("t16ffc", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t16ffc", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t40lp", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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("t40lp", [("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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# 4096x16/18bit can be mapped to a single 2048x32/36bit
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("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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# same for 8192x8/9bit
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("t16ffc", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t16ffc", [("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:RBRAM2"], []),
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("t40lp", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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("t40lp", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_sdp", ["-assert-count 1 t:RBRAM"], ["-nolutram"]),
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# but 4096x20bit requires extra memories because 2048x40bit has 8bit byte enables (which doesn't divide 20bit evenly)
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("t16ffc", [("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_sdp", ["-assert-count 2 t:RBRAM2"], []),
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("t40lp", [("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 20)], "sync_ram_sdp", ["-assert-count 2 t:RBRAM"], ["-nolutram"]),
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]
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@dataclass
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class TestClass:
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params: dict[str, int]
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top: str
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assertions: list[str]
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test_steps: None | list[dict[str, int]]
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opts: list[str]
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tech: str = "t16ffc"
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sim_tests: list[TestClass] = []
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for (tech, params, top, assertions, opts) in inference_tests:
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sim_test = TestClass(
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params=dict(params),
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top=top,
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assertions=assertions,
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test_steps=None,
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opts=opts,
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tech=tech,
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)
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sim_tests.append(sim_test)
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i = 0
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j = 0
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max_j = 16
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f = None
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for sim_test in sim_tests:
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# format params
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param_str = ""
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for (key, val) in sim_test.params.items():
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param_str += f" -set {key} {val}"
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# resolve top module wildcards
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top_list = [sim_test.top]
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if "*dp" in sim_test.top:
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top_list += [
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sim_test.top.replace("*dp", dp_sub) for dp_sub in ["sdp", "tdp"]
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]
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if "w*r" in sim_test.top:
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top_list += [
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sim_test.top.replace("w*r", wr_sub) for wr_sub in ["wwr", "wrr"]
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]
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if len(top_list) > 1:
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top_list.pop(0)
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# iterate over string substitutions
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for top in top_list:
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# limit number of tests per file to allow parallel make
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if not f:
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fn = f"t_mem{i}.ys"
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f = open(fn, mode="w")
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j = 0
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# output yosys script test file
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print(
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blockram_template.format(param_str=param_str, top=top, tech=sim_test.tech, opts=" ".join(sim_test.opts)),
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file=f
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)
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for assertion in sim_test.assertions:
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print(f"log ** CHECKING CELL COUNTS FOR TEST {top} WITH PARAMS{param_str} ON TECH {sim_test.tech}", file=f)
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print(f"select {assertion}", file=f)
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print("", file=f)
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# increment test counter
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j += 1
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if j >= max_j:
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f = f.close()
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i += 1
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if f:
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f.close()
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@ -1,4 +1,5 @@
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#!/usr/bin/env bash
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set -eu
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python3 mem_gen.py
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source ../../gen-tests-makefile.sh
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generate_mk --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
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generate_mk --yosys-scripts --bash
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@ -22,6 +22,30 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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endmodule // sync_ram_sp
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module sync_ram_sp_nochange #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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else
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sp_nochange
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module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk, write_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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@ -112,6 +136,62 @@ module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1)
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endmodule // sync_ram_sdp_wrr
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module double_sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, USE_TDP=0)
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(
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input wire write_enable_a, clk_a,
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input wire [DATA_WIDTH-1:0] data_in_a,
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input wire [ADDRESS_WIDTH-1:0] address_in_a,
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output wire [DATA_WIDTH-1:0] data_out_a,
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input wire write_enable_b, clk_b,
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input wire [DATA_WIDTH-1:0] data_in_b,
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input wire [ADDRESS_WIDTH-1:0] address_in_b,
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output wire [DATA_WIDTH-1:0] data_out_b
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);
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generate
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if (USE_TDP) begin
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sync_ram_tdp #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH+1)
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) ram (
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.clk_a(clk_a), .clk_b(clk_b),
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.write_enable_a(write_enable_a), .write_enable_b(write_enable_b),
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.write_data_a(data_in_a), .write_data_b(data_in_b),
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.addr_a({1'b0, address_in_a}), .addr_b({1'b1, address_in_b}),
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.read_data_a(data_out_a), .read_data_b(data_out_b)
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);
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end else begin
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sync_ram_sp #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) a_ram (
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.write_enable(write_enable_a),
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.clk(clk_a),
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.data_in(data_in_a),
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.address_in(address_in_a),
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.data_out(data_out_a)
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);
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sync_ram_sp #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) b_ram (
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.write_enable(write_enable_b),
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.clk(clk_b),
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.data_in(data_in_b),
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.address_in(address_in_b),
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.data_out(data_out_b)
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);
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end
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endgenerate
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endmodule // double_sync_ram_sp
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module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10)
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(
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input wire write_enable_a, clk_a,
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