1449 commits

Author	SHA1	Message	Date
Eddie Hung	d087024caf	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-25 12:42:09 -08:00
Eddie Hung	180cb39395	abc9 to contain time call	2019-11-25 12:35:57 -08:00
Eddie Hung	f50b6422b0	abc9 to no longer to clock partitioning, operate on whole modules only	2019-11-25 12:35:38 -08:00
Marcin Kościelnicki	6cdea425b8	clkbufmap: Add support for inverters in clock path.	2019-11-25 20:40:39 +01:00
Eddie Hung	bf1167bc64	Conditioning abc9 on POs not accurate due to cells	2019-11-23 10:26:55 -08:00
Eddie Hung	1851f4b488	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-22 23:01:18 -08:00
Eddie Hung	900c806d4e	Move clkpart into passes/hierarchy	2019-11-22 17:25:53 -08:00
Eddie Hung	bf7d36627e	Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff	2019-11-22 17:00:35 -08:00
Eddie Hung	95af8f56e4	Only action if there is more than one clock domain	2019-11-22 17:00:11 -08:00
Eddie Hung	00d76f6cc4	Replace TODO	2019-11-22 16:58:08 -08:00
Eddie Hung	698854955c	Merge branch 'eddie/clkpart' into xaig_dff	2019-11-22 15:41:48 -08:00
Eddie Hung	84153288bb	Brackets	2019-11-22 15:41:34 -08:00
Eddie Hung	3df191cec5	Entry in Makefile.inc	2019-11-22 15:41:23 -08:00
Eddie Hung	bd56161775	Merge branch 'eddie/clkpart' into xaig_dff	2019-11-22 15:38:48 -08:00
Eddie Hung	856a3dc98d	New 'clkpart' to {,un}partition design according to clock/enable	2019-11-22 15:35:51 -08:00
Eddie Hung	c4ec42ac38	When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ ... Since they should be captured downwards from the owning flop	2019-11-21 16:17:03 -08:00
Eddie Hung	729c6b93e8	endomain -> ctrldomain	2019-11-20 14:32:01 -08:00
Eddie Hung	09ee96e8c2	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-11-19 15:40:39 -08:00
Marcin Kościelnicki	38e72d6e13	Fix #1496.	2019-11-18 04:16:48 +01:00
whitequark	c68722818a	flowmap: when doing mincut, ensure source is always in X, not X̅. ... Fixes #1475.	2019-11-12 00:15:43 +00:00
whitequark	eef32195bd	flowmap: don't break if that creates a k+2 (and larger) LUT either. ... Fixes #1405.	2019-11-11 23:13:00 +00:00
Eddie Hung	2cb2116b4c	Use "abc9_period" attribute for delay target	2019-10-07 15:03:44 -07:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	a5ac33f230	Merge branch 'master' into eddie/abc_to_abc9	2019-10-04 17:53:20 -07:00
Eddie Hung	f0cadb0de8	Fix from merge	2019-10-04 17:52:19 -07:00
Eddie Hung	bbc0e06af3	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-04 17:39:08 -07:00
Eddie Hung	0acc51c3d8	Add temporary abc9 -nomfs and use for synth_xilinx -abc9	2019-10-04 17:35:43 -07:00
Eddie Hung	7959e9d6b2	Fix merge issues	2019-10-04 17:21:14 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
Eddie Hung	549d6ea467	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-10-03 10:55:23 -07:00
Clifford Wolf	0e05424885	Merge pull request #1422 from YosysHQ/eddie/aigmap_select ... Add -select option to aigmap	2019-10-03 11:54:04 +02:00
Eddie Hung	265a655ef9	Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf	2019-10-02 12:43:35 -07:00
Eddie Hung	edc3780723	techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias	2019-09-30 17:20:12 -07:00
Eddie Hung	1b96d29174	No need to punch ports at all	2019-09-30 17:02:20 -07:00
Eddie Hung	390b960c8c	Resolve FIXME on calling proc just once	2019-09-30 16:37:29 -07:00
Eddie Hung	e529872b01	Remove need for $currQ port connection	2019-09-30 16:33:40 -07:00
Eddie Hung	f2f19df2d4	Add -select option to aigmap	2019-09-30 15:26:29 -07:00
Eddie Hung	e0aa772663	Add comment	2019-09-30 15:19:02 -07:00
Eddie Hung	a6994c5f16	scc call on active module module only, plus cleanup	2019-09-30 12:57:19 -07:00
Eddie Hung	8684b58bed	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-30 12:29:35 -07:00
Miodrag Milanović	0d27ffd4e6	Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in ... Open aig frontend as binary file	2019-09-30 17:49:23 +02:00
Eddie Hung	1123c09588	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-29 19:39:12 -07:00
Eddie Hung	8474c5b366	Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)	2019-09-29 11:26:22 -07:00
Eddie Hung	5a4011e8c9	Fix "scc" call inside abc9 to consider all wires	2019-09-29 09:58:00 -07:00
Miodrag Milanovic	3f70c1fd26	Open aig frontend as binary file	2019-09-29 13:22:11 +02:00
Eddie Hung	79b6edb639	Big rework; flop info now mostly in cells_sim.v	2019-09-28 23:48:17 -07:00
Eddie Hung	313d2478e9	Split ABC9 based on clocking only, add "abc_mergeability" attr for en	2019-09-27 18:41:04 -07:00
Eddie Hung	fe722b737c	Add -select option to aigmap	2019-09-27 17:44:01 -07:00
Eddie Hung	8f5710c464	Merge remote-tracking branch 'origin/master' into xaig_dff	2019-09-27 15:14:31 -07:00