4293 commits

Author	SHA1	Message	Date
Eddie Hung	cf9e017127	Add xilinx_srl_fixed, fix typos	2019-08-26 14:20:06 -07:00
Eddie Hung	a098205479	Merge branch 'master' into mwk/xilinx_bufgmap	2019-08-26 13:25:17 -07:00
Eddie Hung	7911143827	Create new $__XILINX_SHREG_ cell for variable length too	2019-08-23 18:15:49 -07:00
Eddie Hung	a048fc93e8	Do not allow Q of last cell of variable length SRL to be (* keep *)	2019-08-23 18:15:24 -07:00
Eddie Hung	ee9f6e6243	Also add first.Q to chain_bits since variable length	2019-08-23 18:14:06 -07:00
Eddie Hung	70ce3d0670	Do not enforce !EN_POLARITY on $dffe	2019-08-23 18:11:28 -07:00
Eddie Hung	188b49378a	Create new cell for fixed length SRL	2019-08-23 17:25:30 -07:00
Eddie Hung	e081303ee8	Cleanup FDRE matching	2019-08-23 17:23:52 -07:00
Eddie Hung	54488cfb82	Oops don't need a finally block	2019-08-23 16:39:37 -07:00
Eddie Hung	83e2d87fb8	Keep track of bits in variable length chain, to check for taps	2019-08-23 16:21:10 -07:00
Eddie Hung	f2d4814284	Don't forget $dff has no EN	2019-08-23 16:14:57 -07:00
Eddie Hung	2217d926a9	Same for variable length	2019-08-23 16:13:16 -07:00
Eddie Hung	b1caf7be5e	Filter on en_port for fixed length	2019-08-23 16:09:46 -07:00
Eddie Hung	513af10d77	Check clock is consistent	2019-08-23 15:18:26 -07:00
Eddie Hung	c762618783	Fix last_cell.D	2019-08-23 15:08:49 -07:00
Eddie Hung	ca5de78e76	Revert "Add a unique argument to pmgen's nusers()" ... This reverts commit 1d88887cfd.	2019-08-23 15:04:00 -07:00
Eddie Hung	e85e6e8d45	Revert "Fix polarity" ... This reverts commit 9cd23cf0fe.	2019-08-23 15:03:42 -07:00
Eddie Hung	9cd23cf0fe	Fix polarity	2019-08-23 14:49:34 -07:00
Eddie Hung	c2757613b6	Check for non unique nusers/fanouts	2019-08-23 14:32:36 -07:00
Eddie Hung	1d88887cfd	Add a unique argument to pmgen's nusers()	2019-08-23 14:32:17 -07:00
Eddie Hung	8ecfd55d5a	Update doc	2019-08-23 14:16:41 -07:00
Eddie Hung	3d7f4aa0c8	Remove (* init *) entry when consumed into SRL	2019-08-23 13:56:01 -07:00
Eddie Hung	48c424e45b	Cleanup	2019-08-23 13:46:05 -07:00
Eddie Hung	967a36c125	indo -> into	2019-08-23 13:16:50 -07:00
Eddie Hung	a1f78eab04	indo -> into	2019-08-23 13:15:41 -07:00
Eddie Hung	5939ffdc07	Forgot to slice	2019-08-23 13:06:59 -07:00
Eddie Hung	242b3083ea	Cope with possibility that D could connect to Q on same cell	2019-08-23 13:06:31 -07:00
Eddie Hung	18b64609c2	xilinx_srl to use 'slice' features of pmgen for word level	2019-08-23 12:22:06 -07:00
Eddie Hung	f4fd41d5d2	Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl	2019-08-23 11:35:06 -07:00
Eddie Hung	78b7d8f531	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-23 11:32:44 -07:00
Eddie Hung	d672b1ddec	Merge remote-tracking branch 'origin/master' into xaig_arrival	2019-08-23 11:26:55 -07:00
Eddie Hung	619f2414e5	clkbufmap to only check clkbuf_inhibit if no selection given	2019-08-23 11:14:42 -07:00
Eddie Hung	4d89c3f468	Review comment from @cliffordwolf	2019-08-23 10:03:41 -07:00
Eddie Hung	6872805a3e	Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap	2019-08-23 10:00:50 -07:00
Clifford Wolf	55bf8f69e0	Fix port hanlding in pmgen ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:26:54 +02:00
Clifford Wolf	adb81ba386	Add pmgen slices and choices ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-23 16:15:50 +02:00
Eddie Hung	51ffb093b5	In sat: 'x' in init attr should not override constant	2019-08-22 16:43:08 -07:00
Eddie Hung	2b37a093e9	In sat: 'x' in init attr should not override constant	2019-08-22 16:42:19 -07:00
Eddie Hung	53fed4f7e9	Actually, there might not be any harm in updating sigmap...	2019-08-22 16:16:56 -07:00
Eddie Hung	cfafd360d5	Add comment as per @cliffordwolf	2019-08-22 16:16:56 -07:00
Eddie Hung	8691596d19	Revert "Try way that doesn't involve creating a new wire" ... This reverts commit 2f427acc9e.	2019-08-22 16:16:34 -07:00
Eddie Hung	5ff75b1cdc	Try way that doesn't involve creating a new wire	2019-08-22 16:16:34 -07:00
Eddie Hung	e1fff34dde	If d_bit already in sigbit_chain_next, create extra wire	2019-08-22 16:16:34 -07:00
Eddie Hung	c50d68653d	Spelling	2019-08-22 16:06:36 -07:00
Eddie Hung	6e8fda8bf0	Add doc	2019-08-22 11:52:24 -07:00
Eddie Hung	cabadb85e2	Add copyright	2019-08-22 11:25:19 -07:00
Eddie Hung	36d94caec1	Remove shregmap -tech xilinx additions	2019-08-22 11:22:09 -07:00
Eddie Hung	9f3ed1726e	pmgen to also iterate over all module ports	2019-08-22 11:15:16 -07:00
Eddie Hung	74bd190d3b	Remove output_bits	2019-08-22 11:14:59 -07:00
Eddie Hung	231ddbf95c	Forgot to set ud_variable.minlen	2019-08-22 11:02:17 -07:00