mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity
15792 commits 122 branches 59 tags 72 MiB
Commit graph

20 commits

Author SHA1 Message Date
Marcelina Kościelnicka
aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung
4a10c87ae1 ice40: split out cells_map.v into ff_map.v 2020-05-14 10:33:56 -07:00
Eddie Hung
ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Eddie Hung
ed3f359175 $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve 
name and attr
 2019-12-03 14:49:10 -08:00
Eddie Hung
8a2480526f Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER 2019-08-12 12:19:25 -07:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung
675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung
6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung
5fb27c071b $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
Eddie Hung
c6e16e1334 _ABC macro will map and unmap to this new box 2019-07-12 00:51:37 -07:00
Eddie Hung
4da25c76b3 Ooopsie 2019-06-03 09:33:42 -07:00
Eddie Hung
437fec0d88 Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
Eddie Hung
c1ebe51a75 Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 
This reverts commit a7632ab332.
 2019-04-17 11:10:20 -07:00
Eddie Hung
a7632ab332 Try using an ICE40_CARRY_LUT primitive to avoid ABC issues 2019-04-17 11:10:04 -07:00
Tim 'mithro' Ansell
d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Clifford Wolf
234726c655 Add "synth_ice40 -vpr" 2017-11-16 21:37:02 +01:00
Clifford Wolf
0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf
42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00