mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity
14722 commits 124 branches 59 tags 44 MiB
Commit graph

4281 commits

Author SHA1 Message Date
Keith Rothman
4c82ddf394 Add -params mode to force undef parameters in selected cells. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-21 10:16:38 -08:00
Clifford Wolf
0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix 
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
 2019-02-21 18:58:44 +01:00
Clifford Wolf
893194689d Fix typo in passes/pmgen/README.md 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 18:50:02 +01:00
Eddie Hung
be061810d7 Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig 2019-02-21 09:31:17 -08:00
Clifford Wolf
2da4c9c8f0 Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:49:45 +01:00
Clifford Wolf
2fe1c830eb Bugfix in ice40_dsp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:28:46 +01:00
Eddie Hung
7f26043caf ABC -> ABC9 2019-02-20 17:36:57 -08:00
Eddie Hung
e5b8bb9faa abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_ 2019-02-20 17:33:35 -08:00
Eddie Hung
32853b1f8d lut/not/and suffix to be ${lut,not,and} 2019-02-20 16:30:30 -08:00
Eddie Hung
2ca83005fb abc9 to cope with multiple modules 2019-02-20 12:56:15 -08:00
Eddie Hung
d6b317b349 abc9 to use & syntax for -fast, and name fixes 2019-02-20 12:40:17 -08:00
Clifford Wolf
218e9051bb Add "synth_ice40 -dsp" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:42:27 +01:00
Clifford Wolf
246391200e Add FF support to wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:36:42 +01:00
Clifford Wolf
dca65d83a0 Detect and reject cases that do not map well to iCE40 DSPs (yet) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 11:18:19 +01:00
Eddie Hung
62e5ff9ba8 abc9 to cope with indexed wires when creating $lut from $_NOT_ 2019-02-19 16:06:03 -08:00
Jim Lawson
5c4a72c43e Fix normal (non-array) hierarchy -auto-top. 
Add simple test.
 2019-02-19 14:35:15 -08:00
Eddie Hung
8158bc3f99 abc9 to replace $_NOT_ with $lut 2019-02-19 12:30:20 -08:00
Clifford Wolf
5a853ed46c Add actual DSP inference to ice40_dsp pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-17 15:35:48 +01:00
Clifford Wolf
c06c062469 Merge branch 'master' of github.com:YosysHQ/yosys into pmgen 2019-02-17 12:10:19 +01:00
Eddie Hung
45d49d5d14 Get rid of debugging stuff in abc9 2019-02-16 22:25:22 -08:00
Eddie Hung
f853b2f3c1 abc9 to write_aiger with -O option, and ignore dummy outputs 2019-02-16 20:09:40 -08:00
Eddie Hung
d8c4d4e6c7 abc9 to handle comb loops, cope with constant outputs, disconnect using new wire 2019-02-16 13:47:38 -08:00
Eddie Hung
e7c7ab8fc0 expose command to not skip 'internal' wires beginning with '$' 2019-02-16 13:45:17 -08:00
Eddie Hung
d4545d415b abc9 to cope with non-wideports, count cells properly 2019-02-16 08:53:06 -08:00
Eddie Hung
f8d0134598 Move lookup inside if 2019-02-15 15:23:26 -08:00
Eddie Hung
a786ac4d53 Refactor 2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9 Cope with width != 1 when re-mapping cells 2019-02-15 12:55:52 -08:00
Eddie Hung
956ee545c5 abc9 to stitch results with CI/CO properly 2019-02-15 11:52:34 -08:00
Jim Lawson
5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00
Eddie Hung
206f11dca3 Fix stitching 2019-02-13 17:04:23 -08:00
Eddie Hung
f0f5d8a5cc Merge remote-tracking branch 'origin/read_aiger' into xaig 2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee Merge https://github.com/YosysHQ/yosys into xaig 2019-02-13 14:08:31 -08:00
Eddie Hung
87f059adf7 Rip out some more stuff 2019-02-13 10:44:52 -08:00
Eddie Hung
045f7763ae Rip out unused functions in abc9 2019-02-12 16:25:22 -08:00
Eddie Hung
b3341b4abb WIP for ABC with aiger 2019-02-12 09:31:22 -08:00
Eddie Hung
c23e3f0751 Missing headers for Xcode? 2019-02-12 09:24:13 -08:00
Eddie Hung
5a0a5aae4f Compile abc9 2019-02-08 13:58:47 -08:00
Eddie Hung
e25a22015f Copy abc.cc to abc9.cc 2019-02-08 13:23:54 -08:00
David Shah
a4515712cb fsm_opt: Fix runtime error for FSMs without a reset state 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-07 10:35:36 +00:00
David Shah
58c22dae31 abc: Improved recovered netnames, also preserve src on nets with dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah
8524a479b1 abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-06 22:23:13 +01:00
whitequark
58d059ccb7 proc_clean: fix critical typo. 2019-01-23 22:08:38 +00:00
whitequark
95b6c35882 proc_clean: fix fully def check to consider compare/signal length. 
Fixes #790.
 2019-01-18 23:22:19 +00:00
Clifford Wolf
8ddec5d882 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
5216735210 Progress in pmgen, add pmgen README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
55ac030382 Fix pmgen "reject" statement 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
d45379936b Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
1f8e76f993 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
b9545aa0e1 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
ad69c668ce Add mockup .pmg (pattern matcher generator) file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00