Ruben Undheim
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75009ada3c
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Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
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2018-10-12 21:11:36 +02:00 |
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Clifford Wolf
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9850de405a
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Improve Verific importer blackbox handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-07 19:48:55 +02:00 |
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Clifford Wolf
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ed1f0b2577
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Merge pull request #651 from ARandomOWL/stdcells_fix
Fix IdString M in setup_stdcells()
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2018-10-05 09:59:57 +02:00 |
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Clifford Wolf
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115ca57647
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Add "write_edif -attrprop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-05 09:41:30 +02:00 |
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Clifford Wolf
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257a846113
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Merge pull request #654 from mithro/patch-1
Fix misspelling in issue_template.md
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2018-10-05 09:29:26 +02:00 |
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Clifford Wolf
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4b0448fc2c
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Fix compiler warning in verific.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-05 09:26:10 +02:00 |
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Tim Ansell
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63d53006cb
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Fix misspelling in issue_template.md
It's been bugging me :-P
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2018-10-04 17:15:30 -07:00 |
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Adrian Wheeldon
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1355492c89
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Fix IdString M in setup_stdcells()
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2018-10-04 15:36:26 +01:00 |
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Clifford Wolf
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5f1fea08d5
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Add inout ports to cells_xtra.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-04 11:30:55 +02:00 |
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Clifford Wolf
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bed6c26a6e
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Merge pull request #650 from mithro/patch-1
xilinx: Adding missing inout IO port to IOBUF
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2018-10-04 11:30:00 +02:00 |
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Tim Ansell
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ad975fb694
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xilinx: Adding missing inout IO port to IOBUF
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2018-10-03 16:38:32 -07:00 |
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Clifford Wolf
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76baae4b94
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Merge pull request #645 from daveshah1/ecp5_dram_fix
ecp5: Don't map ROMs to DRAM
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2018-10-02 10:00:10 +02:00 |
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Clifford Wolf
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0a7751a11b
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Merge pull request #646 from tomverbeure/issue594
Fix for issue 594.
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2018-10-02 09:51:44 +02:00 |
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Tom Verbeure
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cb214fc01d
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Fix for issue 594.
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2018-10-02 07:44:23 +00:00 |
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Dan Gisselquist
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62424ef3de
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Add read_verilog $changed support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-01 19:41:35 +02:00 |
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David Shah
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fcd39e1398
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ecp5: Don't map ROMs to DRAM
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-10-01 18:34:41 +01:00 |
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Clifford Wolf
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4d2917447c
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Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
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2018-09-30 18:44:07 +02:00 |
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Clifford Wolf
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9f9fe94b35
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Fix handling of $past 2nd argument in read_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-30 18:43:35 +02:00 |
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Clifford Wolf
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ac4000d855
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Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
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2018-09-28 17:20:43 +02:00 |
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Clifford Wolf
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031824e38c
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Update to v2 YosysVS template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-28 17:20:16 +02:00 |
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Clifford Wolf
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8fde05dfa5
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Add "read_verilog -noassert -noassume -assert-assumes"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-24 20:51:16 +02:00 |
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Clifford Wolf
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eb452ffb28
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Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-23 10:32:54 +02:00 |
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Clifford Wolf
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9659f7a99e
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Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc
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2018-09-23 10:04:37 +02:00 |
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Clifford Wolf
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138ba71264
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Update CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-23 09:25:40 +02:00 |
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Miodrag Milanovic
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41affeeeb9
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added prefix to FDirection constants, fixing windows build
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2018-09-21 20:43:49 +02:00 |
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Clifford Wolf
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2867bf46a9
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Update CHANGLELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-21 16:27:07 +02:00 |
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Clifford Wolf
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bf189122a8
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Update Changelog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-21 13:55:20 +02:00 |
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Clifford Wolf
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dc77ed1e88
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Merge pull request #633 from mmicko/master
Fix Cygwin build and document needed packages
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2018-09-19 15:08:31 +02:00 |
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Clifford Wolf
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f1972b6c90
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Merge pull request #631 from acw1251/master
Fixed typo in "verilog_write" help message
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2018-09-19 15:07:28 +02:00 |
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Miodrag Milanovic
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c5e9034834
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Fix Cygwin build and document needed packages
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2018-09-19 10:16:53 +02:00 |
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acw1251
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efac8a45a6
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Fixed typo in "verilog_write" help message
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2018-09-18 13:34:30 -04:00 |
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Clifford Wolf
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592a82c0ad
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Merge pull request #625 from aman-goel/master
Minor revision to -expose in setundef pass
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2018-09-14 12:36:13 +02:00 |
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Clifford Wolf
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1936d4408e
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Merge pull request #627 from acw1251/master
Fixed minor typo in "sim" help message
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2018-09-14 12:34:51 +02:00 |
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acw1251
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5fe16c25b8
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Fixed minor typo in "sim" help message
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2018-09-12 18:34:27 -04:00 |
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Aman Goel
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75c1f8d241
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Minor revision to -expose in setundef pass
Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
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2018-09-10 21:44:36 -04:00 |
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Clifford Wolf
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51f1bbeeb0
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Add iCE40 SB_SPRAM256KA simulation model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-10 11:57:24 +02:00 |
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Clifford Wolf
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12440fcc8f
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Add $lut support to Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-06 00:18:01 +02:00 |
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Clifford Wolf
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5d9d22f66d
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Add "verific -L <int>" option
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-09-04 20:06:10 +02:00 |
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Clifford Wolf
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0b7a18470b
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Add "make ystests"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-08-30 12:26:26 +02:00 |
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Miodrag Milanović
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d36d11936f
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Add GCC to osx deps (#620)
* Add GCC to osx deps
* Force gcc-7 install
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2018-08-28 17:17:33 +02:00 |
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Clifford Wolf
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cf2ea21899
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Merge pull request #619 from mmicko/master
Remove mercurial, since it is not needed anymore
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2018-08-28 13:37:11 +02:00 |
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Miodrag Milanovic
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92896a58be
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Remove mercurial, since it is not needed anymore
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2018-08-28 13:11:41 +02:00 |
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Clifford Wolf
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373244c5ab
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Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes
Add support for modules.
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2018-08-28 12:04:49 +02:00 |
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Jim Lawson
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e217c6c52f
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Merge branch 'master' into firrtl+modules+shiftfixes
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2018-08-27 12:13:04 -07:00 |
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Jim Lawson
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380c6f0e97
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Remove unused functions.
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2018-08-27 10:18:33 -07:00 |
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Jim Lawson
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604b5d4e20
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Merge pull request #3 from YosysHQ/master
merge with YosysHQ
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2018-08-27 10:09:39 -07:00 |
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Clifford Wolf
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ddc1761f1a
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Add "make coverage"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-08-27 14:22:21 +02:00 |
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Clifford Wolf
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9e845bd254
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Add ENABLE_GCOV build option
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-08-27 13:27:05 +02:00 |
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Clifford Wolf
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96d79878b9
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Merge pull request #617 from mmicko/master
static link flag on main executable
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2018-08-25 16:40:55 +02:00 |
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Miodrag Milanovic
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306a010e19
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static link flag on main executable
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2018-08-25 16:20:44 +02:00 |
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