Udi Finkelstein
80d9d15f1c
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
...
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
Udi Finkelstein
e951ac0dfb
$size() now works correctly for all cases!
...
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
...
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
Udi Finkelstein
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Clifford Wolf
080004b19a
Fixed typo in tests/simple/arraycells.v
2017-01-04 12:39:01 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Eric Smith
f4240cc8a4
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
Clifford Wolf
450f6f59b4
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
Clifford Wolf
cdd0b85e47
Added another mem2reg test case
2016-08-21 13:45:46 +02:00
Clifford Wolf
82a4a0230f
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
Clifford Wolf
9a101dc1f7
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
Clifford Wolf
7a4ee5da74
Fixed init issue in mem2reg_test2 test case
2016-06-17 20:15:11 +02:00
Clifford Wolf
11f7b8a2a1
Added opt_expr support for div/mod by power-of-two
2016-05-29 12:17:36 +02:00
Clifford Wolf
1761d08dd2
Bugfix and improvements in memory_share
2016-04-21 14:22:58 +02:00
Clifford Wolf
0f94902125
Added tests/simple/graphtest.v
2015-11-30 11:41:12 +01:00
Clifford Wolf
7ae3d1b5a9
More bugfixes in handling of parameters in tasks and functions
2015-11-12 13:02:36 +01:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
ddf3e2dc65
Bugfix in memory_dff
2015-10-31 22:01:41 +01:00
Clifford Wolf
ccdbf41be6
Improvements in wreduce
2015-10-31 13:39:30 +01:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
913c304fe6
Added $meminit test case
2015-02-14 11:26:20 +01:00
Clifford Wolf
694cc01f1d
improvements in muxtree/select_leaves test
2015-01-18 13:24:01 +01:00
Clifford Wolf
f630868bc9
Improvements in opt_muxtree
2015-01-18 12:57:36 +01:00
Clifford Wolf
f9c096eeda
Added support for task and function args in parentheses
2014-10-27 13:21:57 +01:00
Clifford Wolf
cad98bcd89
Added multi-dim memory test (requires iverilog git head)
2014-08-12 10:37:47 +02:00
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
Clifford Wolf
0129d41efa
Fixed AST handling of variables declared inside a functions main block
2014-08-05 08:35:51 +02:00
Clifford Wolf
7d98645fe8
Added "make -j{N}" support to "make test"
2014-07-30 19:23:26 +02:00
Clifford Wolf
27a872d1e7
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
Clifford Wolf
50f22ff30c
Renamed some of the test cases in tests/simple to avoid name collisions
2014-07-25 13:01:45 +02:00
Clifford Wolf
9b183539af
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
Clifford Wolf
5867f6bcdc
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
Clifford Wolf
6d69d4aaa8
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
Clifford Wolf
964a67ac41
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
Clifford Wolf
ee8ad72fd9
fixed parsing of constant with comment between size and value
2014-07-02 06:27:04 +02:00
Clifford Wolf
076182c34e
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
Clifford Wolf
3345fa0bab
Little steps in realmath test bench
2014-06-21 21:43:04 +02:00
Clifford Wolf
df76da8fd7
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:49:59 +02:00
Clifford Wolf
398482eced
Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
2014-06-15 09:39:22 +02:00
Clifford Wolf
a4ec19c25c
Added tests/realmath to "make test"
2014-06-15 09:31:03 +02:00
Clifford Wolf
f3b4a9dd24
Added support for math functions
2014-06-14 13:36:23 +02:00
Clifford Wolf
406f86a91e
Added realexpr.v test case
2014-06-14 12:01:17 +02:00
