Clifford Wolf
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739c621330
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Merge pull request #1402 from YosysHQ/clifford/portlist
Add "portlist" command
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2019-09-25 09:20:54 +02:00 |
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Clifford Wolf
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b432c9b44b
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Improve "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-25 09:20:38 +02:00 |
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Clifford Wolf
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6c427d36dd
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Add "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-24 18:08:59 +02:00 |
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Miodrag Milanović
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057dae4f78
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Merge pull request #1399 from nakengelhardt/fix-show-macos
fix show command for macos
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2019-09-23 20:06:40 +02:00 |
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N. Engelhardt
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2b81ce5648
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add xdot dependency to Brewfile
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2019-09-23 18:25:04 +02:00 |
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N. Engelhardt
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3bed4cb18a
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fix show command for macos
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2019-09-23 17:47:05 +02:00 |
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Clifford Wolf
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0a2d8db793
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Merge pull request #1392 from YosysHQ/eddie/fix1391
(* techmap_autopurge *) fixes when ports aren't consistently-sized
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2019-09-21 11:25:36 +02:00 |
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Eddie Hung
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7c8de1dd18
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Hell let's add the original #1381 testcase too
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2019-09-20 17:58:51 -07:00 |
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Eddie Hung
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ec08a031b5
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Revert abc9.cc
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2019-09-20 17:52:23 -07:00 |
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Eddie Hung
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6258e6a7e2
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Add testcase
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2019-09-20 17:51:45 -07:00 |
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Eddie Hung
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72ce06909e
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Trim mismatched connection to be same (smallest) size
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2019-09-20 17:51:36 -07:00 |
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Eddie Hung
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567e5f0aa7
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Fix first testcase in #1391
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2019-09-20 17:51:27 -07:00 |
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Clifford Wolf
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f3781f98db
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Merge pull request #1386 from YosysHQ/clifford/fix1360
Fix handling of read_verilog config in AstModule::reprocess_module()
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2019-09-20 13:30:28 +02:00 |
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Clifford Wolf
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8da0888bf6
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Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-20 12:16:20 +02:00 |
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Clifford Wolf
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c072e00a39
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Update CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-20 10:28:20 +02:00 |
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Clifford Wolf
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1f64b34c64
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Add "add -mod"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-20 10:27:17 +02:00 |
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Clifford Wolf
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db17833a5f
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Merge pull request #1384 from YosysHQ/clifford/fix1381
Add techmap_autopurge attribute
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2019-09-20 09:58:42 +02:00 |
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Clifford Wolf
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b76fac3ac3
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Add techmap_autopurge attribute, fixes #1381
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-19 20:00:52 +02:00 |
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Marcin Kościelnicki
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13fa873f11
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Use extractinv for synth_xilinx -ise
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2019-09-19 04:02:48 +02:00 |
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Marcin Kościelnicki
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c9f9518de4
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Added extractinv pass
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2019-09-19 04:02:48 +02:00 |
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Eddie Hung
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70c607d7dd
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Document (* gentb_skip *) attr for test_autotb
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2019-09-18 12:41:35 -07:00 |
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Eddie Hung
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b66c99ece0
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Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
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2019-09-18 12:40:08 -07:00 |
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Eddie Hung
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3ec28ec53a
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Merge pull request #1379 from mmicko/sim_models
Added simulation models for Efinix and Anlogic
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2019-09-18 10:04:27 -07:00 |
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Miodrag Milanovic
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3e9449cb0b
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make note that it is for latch mode
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2019-09-18 17:48:16 +02:00 |
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Miodrag Milanovic
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b0ca6de472
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better lut handling
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2019-09-18 17:45:19 +02:00 |
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Miodrag Milanovic
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8badd4d812
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better handling of lut and begin/end add
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2019-09-18 17:45:07 +02:00 |
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Clifford Wolf
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779ce3537f
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Add "write_aiger -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-18 13:33:02 +02:00 |
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Clifford Wolf
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b88d2e5f30
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Fix stupid bug in btor back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-18 11:56:14 +02:00 |
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Clifford Wolf
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36df37a734
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Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-16 13:05:41 +02:00 |
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Clifford Wolf
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861f2af5aa
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Merge pull request #1380 from YosysHQ/clifford/fix1372
Fix handling of range selects on loop variables
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2019-09-16 13:05:02 +02:00 |
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Clifford Wolf
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25b08b1afd
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Fix handling of range selects on loop variables, fixes #1372
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-16 11:25:37 +02:00 |
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Eddie Hung
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2b93b8fc74
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Merge pull request #1374 from YosysHQ/eddie/fix1371
Fix two non-deterministic behaviours that cause divergence between compilers
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2019-09-15 13:56:07 -07:00 |
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Marcin Kościelnicki
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09ac36da60
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xilinx: Make blackbox library family-dependent.
Fixes #1246.
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2019-09-15 13:37:24 +02:00 |
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Clifford Wolf
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d9f99745da
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Merge pull request #1377 from YosysHQ/clifford/fixzdigit
Fix handling of z_digit "?" and fix optimization of cmp with "z"
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2019-09-15 11:04:31 +02:00 |
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Miodrag Milanovic
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3487b95224
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Added simulation models for Efinix and Anlogic
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2019-09-15 09:37:16 +02:00 |
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Eddie Hung
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f492567c87
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Oops
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2019-09-13 18:19:07 -07:00 |
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Eddie Hung
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a2eee9ebef
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Add counter-example from @cliffordwolf
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2019-09-13 16:41:10 -07:00 |
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Eddie Hung
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14d72c39c3
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Revert "Make one check $shift(x)? only; change testcase to be 8b"
This reverts commit e2c2d784c8.
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2019-09-13 16:33:18 -07:00 |
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Eddie Hung
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9a84e4711c
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Spacing
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2019-09-13 16:30:44 -07:00 |
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Eddie Hung
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9a73adde50
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Explicitly order function arguments
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2019-09-13 16:18:05 -07:00 |
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Eddie Hung
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5473e597bf
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Use template specialisation
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2019-09-13 11:13:57 -07:00 |
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Eddie Hung
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95e80809a5
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Revert "SigSet<Cell*> to use stable compare class"
This reverts commit 4ea34aaacd.
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2019-09-13 09:49:15 -07:00 |
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Clifford Wolf
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a67d63714b
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Fix handling of z_digit "?" and fix optimization of cmp with "z"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-13 13:39:39 +02:00 |
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Clifford Wolf
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4da6e19fe1
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Merge pull request #1373 from YosysHQ/clifford/fix1364
Fix lexing of integer literals
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2019-09-13 10:22:34 +02:00 |
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Clifford Wolf
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855e6a9b91
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Fix lexing of integer literals without radix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-13 10:19:58 +02:00 |
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Eddie Hung
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c487a8ff25
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Grammar
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2019-09-12 12:00:34 -07:00 |
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Eddie Hung
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c05a403dd1
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static_assert to enforce this going forward
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2019-09-12 11:45:17 -07:00 |
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Eddie Hung
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4ea34aaacd
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SigSet<Cell*> to use stable compare class
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2019-09-12 11:45:02 -07:00 |
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David Shah
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6044fff074
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Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
Add equiv_opt -multiclock
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2019-09-12 12:26:28 +01:00 |
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Clifford Wolf
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7eb593829f
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Fix lexing of integer literals, fixes #1364
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-09-12 09:43:32 +02:00 |
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