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Code Activity
8437 commits 124 branches 59 tags 44 MiB
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1724 commits

Author SHA1 Message Date
Eddie Hung
72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung
152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung
b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map 
Cleanup +/xilinx/arith_map.v
 2020-01-18 09:11:52 -08:00
David Shah
a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning 
ice40: Demote conflicting FF init values to a warning
 2020-01-18 09:47:17 +00:00
Eddie Hung
78ffd5d193 synth_ice40: call wreduce before mul2dsp 2020-01-17 15:41:55 -08:00
Eddie Hung
5c589244df Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
Eddie Hung
1e6d56dca1 +/xilinx/arith_map.v fix $lcu rule 2020-01-17 11:28:37 -08:00
Miodrag Milanović
abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W 
synth_xilinx: fix default W value for non-xc7
 2020-01-15 08:47:16 +01:00
Eddie Hung
36d1a2c60f synth_xilinx: fix default W value for non-xc7 2020-01-14 11:34:40 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung
ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung
c0b55deb0b synth_ice40: -abc2 to always use abc even if -abc9 2020-01-12 11:26:05 -08:00
Eddie Hung
35e49fde4d Another conflict 2020-01-11 18:57:25 -08:00
Eddie Hung
c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Eddie Hung
7d94e18100 synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro 2020-01-10 15:07:46 -08:00
Miodrag Milanovic
992b507537 Use CARRY4 for abc1 as well, preventing issues with Vivado 2020-01-10 12:34:21 +01:00
Eddie Hung
823a08e0d8 Fix abc9_xc7.box comments 2020-01-07 17:00:38 -08:00
Eddie Hung
6e3e814025 Fix abc9_xc7.box comments 2020-01-07 15:59:18 -08:00
Eddie Hung
94ab3791ce Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs 2020-01-07 15:44:18 -08:00
Eddie Hung
5c89dead5f Merge branch 'master' of github.com:YosysHQ/yosys 2020-01-06 16:51:32 -08:00
Eddie Hung
01866a7909 Fix DSP48E1 sim 2020-01-06 16:45:29 -08:00
Eddie Hung
53aa51dc92 Re-enable &mfs for synth_{ecp5,xilinx} 2020-01-06 16:21:04 -08:00
Eddie Hung
98ee8c14df Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 15:02:44 -08:00
Eddie Hung
66698cb6fd
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor 
Refactor abc9's DSP48E1 handling
 2020-01-06 15:00:16 -08:00
Eddie Hung
28bf712372 Wrap arrival functions inside `YOSYS too 2020-01-06 11:55:56 -08:00
Eddie Hung
27c150bfcc Fix return value of arrival time functions, fix word 2020-01-06 11:39:08 -08:00
Eddie Hung
19541640ee Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-06 09:31:28 -08:00
Miodrag Milanovic
c5d28f5d6b Valid to have attribute starting with SB_CARRY. 2020-01-04 19:00:44 +01:00
Eddie Hung
bac1e65a9c Fix spacing 2020-01-02 17:21:54 -08:00
Eddie Hung
50b68777d3 Drive $[ABCD] explicitly 2020-01-02 13:28:37 -08:00
whitequark
f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming 
Harmonize BRAM/LUTRAM descriptions across all of Yosys
 2020-01-02 21:06:17 +00:00
Eddie Hung
a051801b72 synth_xilinx -dff to work with abc too 2020-01-02 12:53:26 -08:00
Eddie Hung
3012e9eebc Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor 2020-01-02 12:48:07 -08:00
Eddie Hung
b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung
ec1756c094 Update comments 2020-01-02 12:39:52 -08:00
Eddie Hung
8e507bd807 abc9 -keepff -> -dff; refactor dff operations 2020-01-02 12:36:54 -08:00
Eddie Hung
d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime 
"abc -dff" to no longer retime by default
 2020-01-02 08:46:24 -08:00
Eddie Hung
d0d3ab8f67 ifndef __ICARUS__ -> ifdef YOSYS 2020-01-01 17:33:47 -08:00
Eddie Hung
3d98a96273 ifdef __ICARUS__ -> ifndef YOSYS 2020-01-01 17:33:10 -08:00
Eddie Hung
db04161eca Rework abc9's DSP48E1 model 2020-01-01 17:30:26 -08:00
Eddie Hung
3deec51ddc Fix anlogic async flop mapping 2020-01-01 08:43:16 -08:00
Eddie Hung
0e95756e96 Clamp -46ps for FDPE* too 2020-01-01 08:39:00 -08:00
Eddie Hung
c40b1aae42 Restore abc9 -keepff 2020-01-01 08:34:43 -08:00
whitequark
550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys. 
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
 2020-01-01 12:30:00 +00:00
Eddie Hung
44d9fb0e7c Re-arrange FD order 2019-12-31 18:47:38 -08:00
Eddie Hung
f7793a2956 Missing character 2019-12-31 18:42:11 -08:00
Eddie Hung
35c659be74 Cleanup xilinx boxes 2019-12-31 18:29:44 -08:00
Eddie Hung
2358320f51 Cleanup ice40 boxes 2019-12-31 18:29:37 -08:00