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Restore abc9 -keepff
This commit is contained in:
Eddie Hung
parent
ac808c5e2a
commit
c40b1aae42
4 changed files with 43 additions and 125 deletions
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@ -21,7 +21,8 @@
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// The following techmapping rules are intended to be run (with -max_iter 1)
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// before invoking the `abc9` pass in order to transform the design into
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// a format that it understands.
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//
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`ifdef DFF_MODE
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// For example, (complex) flip-flops are expected to be described as an
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// combinatorial box (containing all control logic such as clock enable
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// or synchronous resets) followed by a basic D-Q flop.
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@ -83,7 +84,6 @@ module FDRE (output Q, input C, CE, D, R);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -114,21 +114,9 @@ module FDRE (output Q, input C, CE, D, R);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_R_INVERTED(IS_R_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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);
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`endif
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endmodule
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module FDRE_1 (output Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -153,14 +141,6 @@ module FDRE_1 (output Q, input C, CE, D, R);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDRE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
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);
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`endif
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endmodule
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module FDSE (output Q, input C, CE, D, S);
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@ -168,7 +148,6 @@ module FDSE (output Q, input C, CE, D, S);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -198,21 +177,9 @@ module FDSE (output Q, input C, CE, D, S);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDSE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_S_INVERTED(IS_S_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .S(S)
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);
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`endif
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endmodule
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module FDSE_1 (output Q, input C, CE, D, S);
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parameter [0:0] INIT = 1'b1;
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`ifdef DFF_MODE
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wire QQ, $Q;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -236,14 +203,6 @@ module FDSE_1 (output Q, input C, CE, D, S);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
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`else
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(* abc9_keep *)
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FDSE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .S(S)
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);
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`endif
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endmodule
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module FDCE (output Q, input C, CE, D, CLR);
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@ -251,7 +210,6 @@ module FDCE (output Q, input C, CE, D, CLR);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -295,21 +253,9 @@ module FDCE (output Q, input C, CE, D, CLR);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
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);
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`endif
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endmodule
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module FDCE_1 (output Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -345,14 +291,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
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);
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`endif
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endmodule
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module FDPE (output Q, input C, CE, D, PRE);
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@ -360,7 +298,6 @@ module FDPE (output Q, input C, CE, D, PRE);
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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`ifdef DFF_MODE
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wire QQ, $Q, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -402,21 +339,9 @@ module FDPE (output Q, input C, CE, D, PRE);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
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);
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`endif
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endmodule
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module FDPE_1 (output Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b1;
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`ifdef DFF_MODE
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wire QQ, $Q, $abc9_currQ;
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generate if (INIT == 1'b1) begin
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assign Q = ~QQ;
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@ -452,15 +377,8 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
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wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
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wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
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`else
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(* abc9_keep *)
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FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
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);
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`endif
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endmodule
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`endif
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// Attach a (combinatorial) black-box onto the output
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// of thes LUTRAM primitives to capture their
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@ -108,7 +108,7 @@ struct SynthXilinxPass : public ScriptPass
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log(" flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc9' with -dff option\n");
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log(" enable sequential synthesis with 'abc9'\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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@ -559,6 +559,8 @@ struct SynthXilinxPass : public ScriptPass
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abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
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else
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abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
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if (!dff_mode)
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abc9_opts += " -keepff";
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run("abc9" + abc9_opts);
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run("techmap -map +/xilinx/abc9_unmap.v");
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}
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