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Author SHA1 Message Date
whitequark
58a5755187
Merge pull request #2554 from hzeller/master 
Fix digit-formatting calculation for small numbers.
 2021-02-25 13:54:16 -08:00
Marcelina Kościelnicka
979347999f btor, smt2, smv: Add a hint on how to deal with funny FF types. 2021-02-25 22:04:04 +01:00
Marcelina Kościelnicka
a651204efa Fix handling of unique/unique0/priority cases in the frontend. 
Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.
 2021-02-25 21:53:58 +01:00
TimRudy
dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) 2021-02-24 15:48:15 -05:00
whitequark
fffbf651df
Merge pull request #2607 from zachjs/logger-error-atexit 
Fix double-free on unmatched logger error pattern
 2021-02-24 19:12:56 +00:00
Zachary Snow
5e439b6e3f Fix double-free on unmatched logger error pattern 
When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.
 2021-02-23 20:49:21 -05:00
Marcelina Kościelnicka
b05b98521c Add tests for some common techmap files. 2021-02-24 01:07:34 +01:00
Marcelina Kościelnicka
cde73428b0 Fix syntax error in adff2dff.v 
Fixes #2600.
 2021-02-24 01:07:34 +01:00
Marcelina Kościelnicka
f4f471f342 frontend: Make helper functions for printing locations. 2021-02-23 23:51:52 +01:00
whitequark
ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width 
verilog: fix sizing of constant args for tasks/functions
 2021-02-23 21:46:16 +00:00
Robert Baruch
4b31223e60 int -> bool 2021-02-23 17:52:43 +01:00
Robert Baruch
7c50b89b24 Adds is_wire to SigBit and SigChunk 
Useful for PYOSYS because Python can't easily check wire against NULL.
 2021-02-23 17:52:43 +01:00
William D. Jones
ae07298a6b machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
William D. Jones
353ace5034 machxo2: Update tribuf test to reflect active-low OE. 2021-02-23 17:39:58 +01:00
William D. Jones
8f1a350f5e machxo2: Add experimental status to help. 2021-02-23 17:39:58 +01:00
William D. Jones
e3974809ec machxo2: Add DCCA and DCMA blackbox primitives. 2021-02-23 17:39:58 +01:00
William D. Jones
a1ea1430b6 machxo2: Fix reversed interpretation of REG_SD config bits. 2021-02-23 17:39:58 +01:00
William D. Jones
4e9def23de machxo2: Tristate is active-low. 2021-02-23 17:39:58 +01:00
William D. Jones
8b14152506 machxo2: Fix typos in FACADE_FF sim model. 2021-02-23 17:39:58 +01:00
William D. Jones
8348c45e4f machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. 2021-02-23 17:39:58 +01:00
William D. Jones
120404bfda machxo2: Improve help_mode output in synth_machxo2. 2021-02-23 17:39:58 +01:00
William D. Jones
3674eb34d4 machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells. 2021-02-23 17:39:58 +01:00
William D. Jones
124780ecd9 machxo2: Add missing OSCH oscillator primitive. 2021-02-23 17:39:58 +01:00
William D. Jones
c31b17a2e2 machxo2: Add believed-to-be-correct tribuf test. 2021-02-23 17:39:58 +01:00
William D. Jones
c7aaa88f58 machxo2: Add passing fsm, mux, and shifter tests. 2021-02-23 17:39:58 +01:00
William D. Jones
453904dd00 machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. 2021-02-23 17:39:58 +01:00
William D. Jones
597a54dbd0 machxo2: Add -noiopad option to synth_machxo2. 2021-02-23 17:39:58 +01:00
William D. Jones
3697f351d5 machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. 2021-02-23 17:39:58 +01:00
William D. Jones
f07b8eb606 machxo2: Fix cells_sim typo where OFX1 was multiply-driven. 2021-02-23 17:39:58 +01:00
William D. Jones
c76f361b56 machxo2: synth_machxo2 now maps ports to FACADE_IO. 2021-02-23 17:39:58 +01:00
William D. Jones
03cbf1327d machxo2: Add initial value for Q in FACADE_FF. 2021-02-23 17:39:58 +01:00
William D. Jones
0364ded385 machxo2: Add FACADE_IO simulation model. More comments on models. 2021-02-23 17:39:58 +01:00
William D. Jones
1b703d3f03 machxo2: Add FACADE_SLICE simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones
cc52eb53cd machxo2: Improve FACADE_FF simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones
427fed23ee machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. 2021-02-23 17:39:58 +01:00
William D. Jones
19b043344c machxo2: Add dffe test. 2021-02-23 17:39:58 +01:00
William D. Jones
84937e9689 machxo2: Add dff.ys test, fix another cells_map.v typo. 2021-02-23 17:39:58 +01:00
William D. Jones
044393b990 machxo2: Fix more oversights in machxo2 models. logic.ys test passes. 2021-02-23 17:39:58 +01:00
William D. Jones
9cb0bae1b2 machxo2: Add test/arch/machxo2 directory (test does not pass). 2021-02-23 17:39:58 +01:00
William D. Jones
b87f6a0906 machxo2: Fix typos. test/arch/run-test.sh passes. 2021-02-23 17:39:58 +01:00
William D. Jones
88c8f81260 machxo2: Create basic techlibs and synth_machxo2 pass. 2021-02-23 17:39:58 +01:00
Karol Gugala
cc7d18d29a frontend: json: parse negative values 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-02-23 00:26:11 +01:00
Marcelina Kościelnicka
4746ffd7b2 assertpmux: Fix crash on unused $pmux output. 
Fixes #2595.
 2021-02-22 23:30:28 +01:00
whitequark
01ccb80b70
Merge pull request #2586 from zachjs/tern-recurse 
verilog: support recursive functions using ternary expressions
 2021-02-21 20:56:04 +00:00
whitequark
3fee43cde0
Merge pull request #2591 from zachjs/verilog-preproc-unapplied 
verilog: error on macro invocations with missing argument lists
 2021-02-21 20:53:56 +00:00
Zachary Snow
b6af90fe20 verilog: fix sizing of constant args for tasks/functions 
- Simplify synthetic localparams for normal calls to update their width
    - This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
    - `eval_const_function` never correctly handled this, but the issue
      was not exposed in the existing tests until the recent change to
      always attempt constant function evaluation when all-const args
      are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
 2021-02-21 15:44:43 -05:00
Zachary Snow
220cb1f7bb verilog: error on macro invocations with missing argument lists 
This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
 2021-02-19 09:18:41 -05:00
Yosys Bot
127484e675 Bump version 2021-02-18 00:10:06 +00:00
Claire Xen
dbaccfbabe
Merge pull request #2590 from RobertBaruch/fix_fast_sop_mode 
Fixes command line for abc pass in -fast -sop mode
 2021-02-17 16:30:12 +01:00
Robert Baruch
1d79222af4 Fixes command line for abc pass in -fast -sop mode 2021-02-16 16:34:09 -08:00