222 commits

Author	SHA1	Message	Date
Clifford Wolf	a6c96b986b	Added Yosys::{dict,nodict,vector} container types	2014-12-26 10:53:21 +01:00
Clifford Wolf	26cbe4a4e5	Fixed constant "cond ? string1 : string2" with strings of different size	2014-10-25 18:23:53 +02:00
Clifford Wolf	750c615e7f	minor indenting corrections	2014-10-19 18:42:03 +02:00
Parviz Palangpour	de8adb8ec5	Builds on Mac 10.9.2 with LLVM 3.5.	2014-10-19 11:14:43 -05:00
Clifford Wolf	35fbc0b35f	Do not the 'z' modifier in format string (another win32 fix)	2014-10-11 11:42:08 +02:00
Clifford Wolf	98442e019d	Added emscripten (emcc) support to build system and some build fixes	2014-08-22 16:20:22 +02:00
Clifford Wolf	085c8e873d	Added AstNode::asInt()	2014-08-21 17:11:51 +02:00
Clifford Wolf	7bfc4ae120	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
Clifford Wolf	38addd4c67	Added support for global tasks and functions	2014-08-21 12:42:28 +02:00
Clifford Wolf	acb435b6cf	Added const folding of AST_CASE to AST simplifier	2014-08-18 00:02:30 +02:00
Clifford Wolf	d491fd8c19	Use stackmap<> in AST ProcessGenerator	2014-08-17 00:57:24 +02:00
Clifford Wolf	c7afbd9d8e	Fixed bug in "read_verilog -ignore_redef"	2014-08-15 01:53:22 +02:00
Clifford Wolf	c83b990458	Changed the AST genWidthRTLIL subst interface to use a std::map	2014-08-14 23:02:07 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	d259abbda2	Added AST_MULTIRANGE (arrays with more than 1 dimension)	2014-08-06 15:52:54 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	bd74ed7da4	Replaced sha1 implementation	2014-08-01 19:01:10 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	c4bdba78cb	Added proper Design->addModule interface	2014-07-27 21:12:09 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	82bbd2f077	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	2014-06-16 15:05:37 +02:00
Clifford Wolf	4d1df128fa	Improved AstNode::realAsConst for large numbers	2014-06-15 09:27:09 +02:00
Clifford Wolf	48dc6ab98d	Improved AstNode::asReal for large integers	2014-06-15 08:38:31 +02:00
Clifford Wolf	149fe83a8d	improved (fixed) conversion of real values to bit vectors	2014-06-14 21:00:51 +02:00
Clifford Wolf	9bd7d5c468	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
Clifford Wolf	442a8e2875	Implemented basic real arithmetic	2014-06-14 08:51:22 +02:00
Clifford Wolf	7ef0da32cd	Added Verilog lexer and parser support for real values	2014-06-13 11:29:23 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	b5cd7a0179	added while and repeat support to verilog parser	2014-06-06 17:40:04 +02:00
Clifford Wolf	09805ee9ec	Include id2ast pointers when dumping AST	2014-03-05 19:56:31 +01:00
Clifford Wolf	4bd25edcd4	Cleanups in handling of read_verilog -defer and -icells	2014-02-20 19:12:32 +01:00
Clifford Wolf	02e6f2c5be	Added Verilog support for "`default_nettype none"	2014-02-17 14:28:52 +01:00
Clifford Wolf	e8af3def7f	Added support for FOR loops in function calls in parameters	2014-02-14 20:33:22 +01:00
Clifford Wolf	534c1a5dd0	Created basic support for function calls in parameter values	2014-02-14 19:56:44 +01:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	88fbdd4916	Fixed algorithmic complexity of AST simplification of long expressions	2014-01-20 20:25:20 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	891e4b5b0d	Keep strings as strings in const ternary and concat	2013-12-05 13:26:17 +01:00
Clifford Wolf	5c39948ead	Added AstNode::mkconst_str API	2013-12-05 12:53:49 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00