Miodrag Milanović
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71d148bcaa
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Merge pull request #1559 from YosysHQ/efinix_test_fix
Fix for non-deterministic test
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2020-01-29 11:18:06 +01:00 |
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Eddie Hung
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d004953772
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Add "help -all" and "help -celltypes" sanity test
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2020-01-28 18:11:34 -08:00 |
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Eddie Hung
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c5971cb16c
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synth_xilinx: cleanup help
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2020-01-28 17:48:43 -08:00 |
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Eddie Hung
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0fd64aab25
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synth_xilinx: fix help when no active_design; fixes #1664
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2020-01-28 17:41:57 -08:00 |
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Marcin Kościelnicki
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7e0e42f907
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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Eddie Hung
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7939727d14
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Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
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2020-01-28 11:55:51 -08:00 |
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Eddie Hung
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6d27d43727
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Add and use SigSpec::reverse()
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2020-01-28 10:37:16 -08:00 |
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Eddie Hung
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245b8c4ab6
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Fix unresolved conflict from #1573
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2020-01-28 10:17:47 -08:00 |
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Miodrag Milanovic
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94191a93dd
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Updated test to use assert-max
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2020-01-28 18:26:10 +01:00 |
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Claire Wolf
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4ddaa70fd6
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Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
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2020-01-28 17:40:28 +01:00 |
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N. Engelhardt
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086c133ea5
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Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
synth_xilinx: error out if tristate without '-iopad'
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2020-01-28 17:24:54 +01:00 |
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Pepijn de Vos
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409e532433
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redirect fuser stderr to /dev/null
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2020-01-28 10:02:41 +01:00 |
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Claire Wolf
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8f40113826
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Merge pull request #1553 from whitequark/manual-dffx
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
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2020-01-28 09:41:08 +01:00 |
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Eddie Hung
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e18aeda7ed
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Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
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2020-01-27 14:02:13 -08:00 |
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Eddie Hung
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cfb0366a18
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Import tests from #1628
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2020-01-27 13:56:16 -08:00 |
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Eddie Hung
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ce6a690d27
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Now done in read_aiger
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2020-01-27 13:30:27 -08:00 |
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Eddie Hung
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48f3f5213e
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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
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2020-01-27 13:29:15 -08:00 |
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Eddie Hung
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9009b76a69
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abc9_ops: add comments
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2020-01-27 11:18:21 -08:00 |
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Eddie Hung
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af8281d2f5
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Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-27 09:54:04 -08:00 |
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Claire Wolf
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07a12ebd4f
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Merge pull request #1658 from YosysHQ/clifford/smtbmcsolvernotfound
Improve yosys-smtbmc "solver not found" handling
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2020-01-27 17:59:58 +01:00 |
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Claire Wolf
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485f31f681
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Improve yosys-smtbmc "solver not found" handling
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-27 17:48:56 +01:00 |
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Claire Wolf
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de6006fbc8
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Merge pull request #1613 from porglezomp-misc/version-flag-alias
Add --version and -version as aliases for -V
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2020-01-27 12:59:27 +01:00 |
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Eddie Hung
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c7fbe13db5
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read_aiger: set abc9_box_seq attr
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2020-01-24 13:11:43 -08:00 |
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Eddie Hung
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81e6b040a4
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ice40: add SB_SPRAM256KA arrival time
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2020-01-24 12:17:09 -08:00 |
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Eddie Hung
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b178761551
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-24 11:59:48 -08:00 |
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Eddie Hung
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dbf351390e
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abc9: -reintegrate recover type from existing cell, check against boxid
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2020-01-23 22:45:34 -08:00 |
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Eddie Hung
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2d795fb8c0
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simple_abc9 tests to discard whitebox before write for sim
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2020-01-23 22:07:43 -08:00 |
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Eddie Hung
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dca1c806ec
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simple_abc9 tests to discard whitebox before write for sim
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2020-01-23 19:55:11 -08:00 |
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Eddie Hung
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e471b330ac
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abc_box_id -> abc9_box_id in test
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2020-01-23 19:12:19 -08:00 |
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Eddie Hung
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245873d42d
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abc9: warning message if no modules selected
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2020-01-23 19:08:51 -08:00 |
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Eddie Hung
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7858cf20a9
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Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
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2020-01-23 19:02:27 -08:00 |
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Eddie Hung
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11e50c0e9e
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Test for (* keep *)-ed abc9_box_id
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2020-01-23 18:56:25 -08:00 |
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Eddie Hung
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f180dba753
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abc9_ops: -prep_xaiger to skip (* keep *) cells
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2020-01-23 18:56:06 -08:00 |
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Eddie Hung
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48aec34e0d
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abc_box_id -> abc9_box_id in test
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2020-01-23 18:53:14 -08:00 |
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Eddie Hung
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1d4314d888
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abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
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2020-01-23 14:58:56 -08:00 |
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Eddie Hung
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af0e7637a2
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alumacc: undo accidental commit
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2020-01-22 20:54:03 -08:00 |
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Eddie Hung
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da134701cd
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Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
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2020-01-22 14:22:03 -08:00 |
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Eddie Hung
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73526a6f10
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read_aiger: also parse abc9_mergeability
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2020-01-22 14:21:25 -08:00 |
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Eddie Hung
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8eb5bb258c
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Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
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2020-01-22 12:30:14 -08:00 |
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Eddie Hung
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da6abc0149
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Merge pull request #1652 from YosysHQ/eddie/abc9_fixes
Eddie/abc9 fixes
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2020-01-22 12:27:41 -08:00 |
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Eddie Hung
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a94b41011d
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abc9: error out if flip-flop init is 1'b1 for '-dff'
Due to ABC sequential synthesis restriction
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2020-01-22 10:08:48 -08:00 |
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Eddie Hung
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3b44b53e94
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abc9: fix scratchpad entry abc9.verify
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2020-01-22 09:36:54 -08:00 |
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Eddie Hung
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3d9737c1bd
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
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2020-01-21 16:27:40 -08:00 |
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Eddie Hung
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cd093c00f8
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read_aiger: discard LUT inputs with nodeID == 0; not < 2
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2020-01-21 11:56:30 -08:00 |
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Eddie Hung
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7f728bc116
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read_aiger: ignore constant inputs on LUTs
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2020-01-21 11:16:50 -08:00 |
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Eddie Hung
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cd8f55a911
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write_xaiger: fix for (* keep *) on flop output
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2020-01-21 09:43:04 -08:00 |
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Claire Wolf
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5791c52e1b
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Merge pull request #1637 from YosysHQ/mwk/fix-1634
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
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2020-01-21 18:37:06 +01:00 |
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Claire Wolf
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30642e9570
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Merge pull request #1629 from YosysHQ/mwk/edif-z
edif: Just ignore connections to 'z
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2020-01-21 18:35:15 +01:00 |
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Claire Wolf
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f165a74824
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Merge pull request #1621 from YosysHQ/clifford/fminit
Add fminit pass
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2020-01-20 22:01:57 +01:00 |
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Eddie Hung
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b7be6cfd65
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Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map
Cleanup +/xilinx/arith_map.v
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2020-01-18 09:11:52 -08:00 |
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