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Author	SHA1	Message	Date
github-actions[bot]	0f9ee20ea2	Bump version	2024-05-04 00:16:00 +00:00
Emil J. Tywoniak	44b0fdc2bf	bbox_derive: add assert and debug print	2024-05-03 20:43:01 +02:00
Emil J. Tywoniak	e8c58a5528	bbox_derive: fix unininitialized memory UB when run with no named args	2024-05-03 20:41:42 +02:00
Martin Povišer	4c000d3aba	Add new bbox_derive command for blackbox derivation	2024-05-03 20:39:11 +02:00
Emil J. Tywoniak	e939182e68	cellmatch: add comments	2024-05-03 16:42:41 +02:00
Martin Povišer	b143e5678f	cellmatch: Rename the special design to $cellmatch	2024-05-03 16:42:41 +02:00
Martin Povišer	913bc87c44	cellmatch: Add test	2024-05-03 16:42:41 +02:00
Martin Povišer	c0e68dcc4d	cellmatch: Add debug print	2024-05-03 16:42:41 +02:00
Martin Povišer	6a9858cdad	cellmatch: Delegate evaluation to ConstEval	2024-05-03 16:42:41 +02:00
Martin Povišer	86e1080f05	cellmatch: New pass	2024-05-03 16:42:41 +02:00
Emil J	2631c7e918	Merge pull request #4365 from widlarizer/techmap-chtype-test ... techmap: add dynamic cell type test	2024-05-03 16:25:42 +02:00
Emil J. Tywoniak	a833f05036	techmap: add dynamic cell type test	2024-05-03 13:53:49 +02:00
Martin Povišer	6ff4ecb2b4	techmap: Remove techmap_chtype from the result	2024-05-03 13:33:28 +02:00
Martin Povišer	fc82251105	techmap: Support dynamic cell types	2024-05-03 13:33:28 +02:00
Akash Levy	2a8575abb2	Update verific to O3 opt	2024-05-03 03:34:36 -07:00
Lofty	8cc9aa7fc6	intel_alm: drop quartus support	2024-05-03 11:32:33 +01:00
Akash Levy	bf8ab97890	Slim yosys	2024-05-03 03:29:42 -07:00
Akash Levy	cc5e893db8	Add noclean option to submod for speedup	2024-05-02 06:12:09 -07:00
Akash Levy	e62bc102ca	Update Verific	2024-05-01 05:43:32 -07:00
Akash Levy	fbf87b2b23	Update Makefile	2024-04-30 05:21:36 -07:00
Akash Levy	810a11b6bc	Fix introduced typo	2024-04-29 22:25:17 -07:00
Akash Levy	8c330c0e4b	Merge branch 'YosysHQ:main' into master	2024-04-29 22:22:47 -07:00
github-actions[bot]	dd2195543b	Bump version	2024-04-30 00:17:14 +00:00
Martin Povišer	640d6a5127	Merge pull request #4359 from georgerennie/aiger_parse_bug ... read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 15:15:43 +02:00
George Rennie	4e6deb53b6	read_aiger: Fix incorrect read of binary Aiger without outputs ... * Also makes all ascii parsing finish reading lines and adds a small test	2024-04-29 14:06:58 +01:00
Jason Wu	f1672b2f14	Update Makefile	2024-04-29 10:16:22 +08:00
Jason Wu	374cd3966d	export define marco to qtcreator.config	2024-04-29 10:04:34 +08:00
Akash Levy	45b723d6f3	Merge branch 'YosysHQ:main' into master	2024-04-25 06:24:57 -07:00
N. Engelhardt	34d9a7451e	Merge pull request #4333 from YosysHQ/fix_hierarchy_generate ... fix hierarchy -generate mode handling of cells	2024-04-25 09:56:24 +02:00
KrystalDelusion	c3ae33da33	Merge pull request #4285 from YosysHQ/typo_fixup ... Typo fixing	2024-04-25 09:54:48 +12:00
Krystine Sherwin	f2ebc3f7b1	github: Add template for documentation issues	2024-04-25 09:39:23 +12:00
Akash Levy	501b5040fa	Merge branch 'YosysHQ:main' into master	2024-04-24 14:20:30 -07:00
Martin Povišer	cd1fb8b157	Merge pull request #4350 from jix/read_rtlil_performance ... rtlil: Add packed `extract` implementation for `SigSpec`	2024-04-24 14:07:28 +02:00
Akash Levy	6d2ac299ba	Merge branch 'YosysHQ:main' into master	2024-04-23 18:15:46 -07:00
github-actions[bot]	cf02f86c28	Bump version	2024-04-24 00:16:06 +00:00
Martin Povišer	982a22da5e	Merge pull request #4351 from povik/bump-abc ... Bump abc	2024-04-23 14:20:54 +02:00
Martin Povišer	67c7062fb8	Bump abc for a fix once more	2024-04-23 13:50:45 +02:00
Martin Povišer	c167d9b76e	Bump abc for one more fix	2024-04-23 11:41:20 +02:00
Martin Povišer	6d6aa4d35e	Bump abc to cherry-pick a WASM build fix	2024-04-22 17:43:41 +02:00
Martin Povišer	4a666d3ba8	Bump abc	2024-04-22 16:39:42 +02:00
Martin Povišer	178eceb32d	rtlil: Replace the packed SigSpec::extract impl	2024-04-22 16:23:51 +02:00
Jannis Harder	0d30a4d479	rtlil: Add packed extract implementation for SigSpec ... Previously `extract` on a `SigSpec` would always unpack it. Since a significant amount of `SigSpec`s have one or few chunks, it's worth having a dedicated implementation. This is especially true, since the RTLIL frontend calls into this for every `wire [lhs:rhs]` slice, making this `extract` take up 40% when profiling `read_rtlil` with one of the largest coarse grained RTLIL designs I had on hand. With this change the `read_rtlil` profile looks like I would expect it to look like, but I noticed that a lot of the other core RTLIL methods also are a bit too eager with unpacking or implementing `SigChunk`/`Const` overloads that just convert to a single chunk `SigSpec` and forward to the implementation for that, when a direct implementation would avoid temporary std::vector allocations. While not relevant for `read_rtlil`, to me it looks like there might be a few easy overall performance gains to be had by addressing this more generally.	2024-04-22 13:26:17 +02:00
Akash Levy	02f38c5df7	Merge branch 'YosysHQ:main' into master	2024-04-21 14:29:49 -07:00
Akash Levy	fa62642b70	Fix BOOST_PYTHON_LIB find	2024-04-19 21:56:11 -07:00
Martin Povišer	171577f909	Merge pull request #4340 from gadfort/abc-lib-merge ... add support for using ABCs library merging when providing multiple liberty files	2024-04-17 22:01:20 +02:00
akash	06ea0372ae	Updated Makefile	2024-04-17 11:19:15 -07:00
akash	04d30773bf	Need to add back in the removed boost python line	2024-04-17 07:21:45 -07:00
Akash Levy	7b12b2867c	Merge branch 'YosysHQ:main' into master	2024-04-17 05:34:30 -07:00
Akash Levy	d3d4077842	Use Preqorsor name so that generated files have correct header	2024-04-17 05:24:25 -07:00
github-actions[bot]	4897e89547	Bump version	2024-04-17 00:16:15 +00:00