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Author	SHA1	Message	Date
Clifford Wolf	d25b6a72ee	Update ABC to hg rev 8da4dc435b9f	2017-02-22 19:20:47 +01:00
Clifford Wolf	242c5f01de	Add "yosys-smtbmc -S <opt>"	2017-02-19 22:51:29 +01:00
Andrew Zonenberg	2eabe43efa	Merge https://github.com/cliffordwolf/yosys	2017-02-16 07:48:44 -08:00
Clifford Wolf	cf25dc9ce7	Copy attributes to _TECHMAP_REPLACE_ cells	2017-02-16 12:28:42 +01:00
Clifford Wolf	e6d56d23b5	Fix eval implementation of $_NOR_	2017-02-16 12:17:03 +01:00
Andrew Zonenberg	6fed2dc996	Merge https://github.com/cliffordwolf/yosys	2017-02-14 08:29:37 -08:00
Clifford Wolf	4fb8007171	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	2017-02-14 15:10:59 +01:00
Clifford Wolf	4e80ce97a8	Add warning about x/z bits left unconnected in EDIF output	2017-02-14 12:49:35 +01:00
Clifford Wolf	2a311c2c38	Fix double-call of log_pop() in synth_greenpak4	2017-02-14 11:57:54 +01:00
Clifford Wolf	f3a25d9d34	Merge pull request #313 from azidar/bugfix-assign-wmask ... More progress on Firrtl backend.	2017-02-14 11:49:14 +01:00
Adam Izraelevitz	794cec0016	More progress on Firrtl backend. ... Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.	2017-02-13 11:17:53 -08:00
Clifford Wolf	69468d5a16	Do not fix port widths on any blackbox instances	2017-02-13 17:07:38 +01:00
Clifford Wolf	db7314bc02	Fix techmap for inout ports connected to inout ports	2017-02-13 16:55:25 +01:00
Clifford Wolf	76c4ee096b	Do not eagerly fix port widths on parameterized cells	2017-02-12 17:42:57 +01:00
Clifford Wolf	828303791b	Add "yosys -w" for suppressing warnings	2017-02-12 11:11:00 +01:00
Andrew Zonenberg	203b521a78	Merge https://github.com/cliffordwolf/yosys	2017-02-11 11:25:16 -08:00
Clifford Wolf	cdb6ceb8c6	Add support for verific mem initialization	2017-02-11 15:57:36 +01:00
Clifford Wolf	c449f4b86f	Fix another stupid bug in the same line	2017-02-11 11:47:51 +01:00
Clifford Wolf	fa4a7efe15	Add verific support for initialized variables	2017-02-11 11:40:18 +01:00
Clifford Wolf	0b7aac645c	Improve handling of Verific warnings and error messages	2017-02-11 11:39:50 +01:00
Clifford Wolf	eb7b18e897	Fix extremely stupid typo	2017-02-11 11:09:07 +01:00
Clifford Wolf	63dfdb5d7f	Add log_wire() API	2017-02-11 11:08:36 +01:00
Clifford Wolf	95dae6d416	Fixed some "used uninitialized" warnings in opt_expr	2017-02-11 10:50:48 +01:00
Clifford Wolf	6d4e8673cc	Evaluate all the $(shell ...) stuff for CXXFLAGS et al only once	2017-02-11 10:28:13 +01:00
Clifford Wolf	a431f4ee31	Merge branch 'stv0g-master'	2017-02-11 10:20:10 +01:00
Clifford Wolf	a1a82d68f5	Make MacOS Makefile stuff more compact	2017-02-11 10:19:21 +01:00
Clifford Wolf	a88e019b0c	Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-master	2017-02-11 10:12:17 +01:00
Clifford Wolf	a5bfeb9e07	Add optimization of (a && 1'b1) and (a || 1'b0)	2017-02-11 10:05:00 +01:00
Clifford Wolf	9c1a7be636	Merge pull request #308 from C-Elegans/opt_compare_fix_pr ... Fix issue #306, "Bug in opt -full"	2017-02-11 10:04:48 +01:00
C-Elegans	94b272077d	Fix issue #306, "Bug in opt -full" ... Add check for whether the high bit in the constant expression is greater than the width of the variable, and optimizes that to a constant 1 or 0	2017-02-10 10:38:02 -05:00
Steffen Vogel	422ffd5c06	Use pkg-config for linking tcl-tk ... Both MacPorts and Homebrew have a pkg-config file for TCL. So lets use it.	2017-02-10 10:06:54 -03:00
Steffen Vogel	9eca3671ab	Dont mix Homebrew and MacPorts build options	2017-02-10 10:04:42 -03:00
Steffen Vogel	a3f19f047c	Remove space after backslash	2017-02-09 19:08:21 -03:00
Steffen Vogel	94c76f85da	Applied fixes from @joshhead (thanks for your effors!)	2017-02-09 18:53:37 -03:00
Clifford Wolf	e6cc67b46f	Fix handling of init attributes with strange width	2017-02-09 16:06:58 +01:00
Clifford Wolf	848062088c	Add checker support to verilog front-end	2017-02-09 13:51:44 +01:00
Clifford Wolf	2ca8d483dd	Add "rand" and "rand const" verific support	2017-02-09 12:53:46 +01:00
Andrew Zonenberg	0d7e71f7ab	Merge https://github.com/cliffordwolf/yosys	2017-02-08 22:12:29 -08:00
Clifford Wolf	ef4a28e112	Add SV "rand" and "const rand" support	2017-02-08 14:38:15 +01:00
Clifford Wolf	1d1f56a361	Add PSL parser mode to verific front-end	2017-02-08 10:40:33 +01:00
Steffen Vogel	b8d531957d	Added notes for compilation on OS X	2017-02-07 11:16:56 -03:00
Steffen Vogel	7e08e37961	Fix compilation on OS X in order to support both MacPorts and Homebrew	2017-02-07 11:16:56 -03:00
Steffen Vogel	19f36271c2	Allow standard tools to be overwritten in make invocation	2017-02-07 11:09:15 -03:00
Clifford Wolf	7e0b776a79	Add "read_blif -wideports"	2017-02-06 14:48:03 +01:00
Clifford Wolf	aab58045a8	Fix undef propagation bug in $pmux SAT model	2017-02-05 22:43:33 +01:00
Clifford Wolf	19303f6392	Update ABC to hg rev a2fcd1cc61a6	2017-02-05 20:04:17 +01:00
Clifford Wolf	1064c8f61f	Merge pull request #304 from esden/gsed-darwin ... Use gsed vs sed on Darwin.	2017-02-05 12:00:21 +01:00
Piotr Esden-Tempski	e3a12b57f5	Use -E sed parameter instead of -r. ... BSD sed equivalent to -r parameter is -E and it is also supported in GNU sed thus using -E results in support on both platforms.	2017-02-04 18:26:01 -08:00
Clifford Wolf	5541b42159	Add assert check in "yosys-smtbmc -c"	2017-02-04 21:22:17 +01:00
Clifford Wolf	adbecfee66	Improve yosys-smtbmc cover() support	2017-02-04 21:10:24 +01:00