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Author SHA1 Message Date
Marcelina Kościelnicka
77b1dfd8c3 opt_mem: Remove constant-value bit lanes. 2022-05-07 23:13:16 +02:00
github-actions[bot]
048170d376 Bump version 2022-05-07 00:15:38 +00:00
Miodrag Milanovic
37b6614718 include latest abc changes 2022-05-06 15:52:24 +02:00
Miodrag Milanovic
7fcf976f9e include latest abc changes 2022-05-06 15:42:39 +02:00
Miodrag Milanović
384d2120ee
Merge pull request #3300 from imhcyx/master 
memory_share: fix wrong argidx in extra_args
 2022-05-06 09:17:59 +02:00
Miodrag Milanovic
52d8ddee0c Include abc change to fix FreeBSD build 2022-05-06 08:08:06 +02:00
Miodrag Milanovic
d8adbff72f Handle possible non-memory indexed data 2022-05-06 08:05:23 +02:00
imhcyx
71166eeecf memory_share: fix wrong argidx in extra_args 2022-05-05 16:58:39 +08:00
github-actions[bot]
a8cc0c3930 Bump version 2022-05-05 00:15:34 +00:00
Marcelina Kościelnicka
18a48b1337 abc: Use dict/pool instead of std::map/std::set 2022-05-04 22:04:50 +02:00
Miodrag Milanovic
8b3657454b map memory location to wire value, if memory is converted to FFs 2022-05-04 13:08:16 +02:00
Miodrag Milanovic
8e02b3ca30 fix crash when no fst input 2022-05-04 11:21:39 +02:00
Miodrag Milanovic
ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Claire Xenia Wolf
3fb32540ea Add propagated clock signals into btor info file 2022-05-04 08:10:18 +02:00
Jannis Harder
96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures 
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
 2022-05-03 14:13:08 +02:00
github-actions[bot]
11e75bc27c Bump version 2022-05-03 00:16:24 +00:00
Miodrag Milanovic
3730db4b98 AIM file could have gaps in or between inputs and inits 2022-05-02 11:18:30 +02:00
github-actions[bot]
c785cb7fe3 Bump version 2022-04-30 00:18:55 +00:00
Miodrag Milanović
7bdf7365e7
Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff 
Ignore merging past ffs that we are not properly merging
 2022-04-29 14:35:46 +02:00
Miodrag Milanovic
422db937d4 Ignore merging past ffs that we are not properly merging 2022-04-29 14:35:02 +02:00
github-actions[bot]
b30d90a14a Bump version 2022-04-26 00:18:47 +00:00
Rick Luiken
414dc25a96 Add missing parameters for ecp5 2022-04-25 15:31:41 +01:00
Jannis Harder
6ae0b51c76
Merge pull request #3287 from jix/smt2-conditional-store 
smt2: Make write port array stores conditional on nonzero write mask
 2022-04-25 16:23:21 +02:00
Jannis Harder
e0e31bfc5c
Merge pull request #3257 from jix/tribuf-formal 
tribuf: `-formal` option: convert all to logic and detect conflicts
 2022-04-25 16:23:06 +02:00
Miodrag Milanović
3c0f3504c6
Merge pull request #3290 from mpasternacki/bugfix/freebsd-build 
Fix build on FreeBSD, which has no alloca.h
 2022-04-25 10:16:50 +02:00
Miodrag Milanović
a511c27eb7
Merge pull request #3289 from YosysHQ/micko/sim_improve 
Simulation improvements
 2022-04-25 10:16:25 +02:00
Maciej Pasternacki
0302e97ebc Fix build on FreeBSD, which has no alloca.h 2022-04-24 19:35:50 +02:00
Miodrag Milanovic
bbfdea2f8a Match $anyseq input if connected to public wire 2022-04-22 17:20:17 +02:00
Miodrag Milanovic
4d80bc24c7 Treat $anyseq as input from FST 2022-04-22 16:23:39 +02:00
Miodrag Milanovic
9c7deabf94 Ignore change on last edge 2022-04-22 15:24:02 +02:00
Miodrag Milanovic
33f4009bb5 Last sample from input does not represent change 2022-04-22 13:46:11 +02:00
Miodrag Milanovic
83cad82b29 latches are always set to zero 2022-04-22 12:04:05 +02:00
Miodrag Milanovic
c989adcc2d If not multiclock, output only on clock edges 2022-04-22 12:03:39 +02:00
Miodrag Milanovic
75032a565d Set init state for all wires from FST and set past 2022-04-22 11:57:39 +02:00
Miodrag Milanovic
8fa2f3b260 Fix multiclock for btor2 witness 2022-04-22 11:53:41 +02:00
Jannis Harder
c7ef0f2932 smt2: Make write port array stores conditional on nonzero write mask 2022-04-20 17:49:48 +02:00
github-actions[bot]
29c0a59589 Bump version 2022-04-19 00:14:02 +00:00
Miodrag Milanović
c3a3f68b4d
Merge pull request #3280 from YosysHQ/micko/fix_readaiw 
Fix reading aiw from other solvers
 2022-04-18 09:49:21 +02:00
Miodrag Milanovic
2610b04033 Update abc 2022-04-18 09:27:00 +02:00
Miodrag Milanovic
1cc281ca6f verific: allow memories to be inferred in loops (vhdl) 2022-04-18 09:10:28 +02:00
Miodrag Milanović
d23260d381
Merge pull request #3282 from nakengelhardt/verific_loop_rams 
verific: allow memories to be inferred in loops
 2022-04-18 09:09:36 +02:00
github-actions[bot]
36b5caf821 Bump version 2022-04-16 00:14:57 +00:00
Marcelina Kościelnicka
25ff83f0b5 memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka
48eea3efcf opt_dff: Fix behavior on $ff with D == Q. 2022-04-15 22:00:32 +02:00
N. Engelhardt
57bc29c64a verific: allow memories to be inferred in loops 2022-04-15 15:10:48 +02:00
Miodrag Milanovic
9508bb2330 Fix reading aiw from other solvers 2022-04-15 11:45:16 +02:00
Jannis Harder
bc48500548 tribuf: -formal option: convert all to logic and detect conflicts 2022-04-12 12:46:22 +02:00
github-actions[bot]
c1646a00ac Bump version 2022-04-09 00:15:22 +00:00
Miodrag Milanović
4772bc70d0
Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix 
Use wrap_async_control_gate if ff is fine
 2022-04-08 17:38:54 +02:00
Miodrag Milanovic
868409361c Use wrap_async_control_gate if ff is fine 2022-04-08 16:30:29 +02:00