mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00
Code Activity
14883 commits 99 branches 53 tags 47 MiB
Commit graph

14883 commits

This branch
This branch
All branches
Author SHA1 Message Date
Akash Levy
35c19cb391 Option to include unused bits attribute or not 2024-08-14 22:05:12 -07:00
github-actions[bot]
1eaf4e0790 Bump version 2024-08-15 00:17:57 +00:00
Akash Levy
34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Akash Levy
71a7f3fabd Fix for segfaulting 2024-08-14 16:00:03 -07:00
Krystine Sherwin
d709177770
test-compile: Downgrade to focal 2024-08-15 09:44:20 +12:00
Akash Levy
8118380726 Update to fix infinite loop 2024-08-14 13:40:30 -07:00
Akash Levy
83dfdd9dd5 Fix splitfanout 2024-08-14 13:19:58 -07:00
Martin Povišer
a854903ff0
Merge pull request #4537 from povik/libparse-cleanup 
Liberty parsing cleanup
 2024-08-14 18:24:51 +02:00
Akash Levy
63a421aed8 Small comment update 2024-08-14 05:37:28 -07:00
Akash Levy
2deabdd640 Make splitfanout more robust 2024-08-14 05:29:03 -07:00
Akash Levy
55782682de Iterative muxpack 2024-08-14 05:27:50 -07:00
Akash Levy
5777bed8ed Add splitfanout first pass 2024-08-14 03:24:24 -07:00
Akash Levy
fd53f4ab1b Better gitignore 2024-08-14 03:24:07 -07:00
Akash Levy
a11ffe3c5c Upstream merge 2024-08-13 13:16:57 -07:00
Martin Povišer
ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer
309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer
3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Martin Povišer
c35f5e379c Extend liberty tests 2024-08-13 18:47:36 +02:00
Martin Povišer
78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
github-actions[bot]
4b9f452735 Bump version 2024-08-13 00:19:11 +00:00
Martin Povišer
8ce6219a34
Merge pull request #4528 from povik/bump-abc 
Bump ABC
 2024-08-12 15:53:16 +02:00
Martin Povišer
bcb995b506 Sync with yosys-experimental branch 2024-08-08 17:33:54 +02:00
Akash Levy
06f5743ac6 Removed submodule 2024-08-08 02:08:01 -07:00
Akash Levy
a66e32d471
Merge branch 'YosysHQ:main' into master 2024-08-08 01:38:27 -07:00
github-actions[bot]
77b2ae2e39 Bump version 2024-08-08 00:18:08 +00:00
Akash Levy
953f405a84
Merge branch 'YosysHQ:main' into master 2024-08-07 11:47:52 -07:00
Martin Povišer
4b5beb635f Pull ABC fix 2024-08-07 17:31:34 +02:00
Martin Povišer
ebffe37e4c Bump ABC 2024-08-07 15:54:03 +02:00
Martin Povišer
b1569de537
Merge pull request #4527 from povik/exec-newline 
exec: Add missing newline
 2024-08-07 13:04:48 +02:00
Martin Povišer
4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
George Rennie
b6ceff2aab peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
George Rennie
236c69bed4 clk2fflogic: run peepopt -formalclk before processing design 
* this attempts to rewrite clock gating patterns into a form that is
  less likely to introduce combinational loops with clk2fflogic

* can be disabled with -nopeepopt which is useful for testing
  clk2fflogic
 2024-08-07 10:14:04 +01:00
George Rennie
2cb3b6e9b8 peepopt: add formal only peepopt to rewrite latches to ffs in clock gates 
* this is gated behind the -formalclk flag, which also disables the other
  synthesis focused optimizations
 2024-08-07 10:01:45 +01:00
github-actions[bot]
669f8b18f0 Bump version 2024-08-07 00:18:20 +00:00
Akash Levy
31d8d5de41
Merge branch 'YosysHQ:main' into master 2024-08-06 03:06:59 -07:00
Akash Levy
68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy
36fb6e08c1 Make muxpack faster 2024-08-06 02:26:57 -07:00
Akash Levy
7f5dcd270d
Merge branch 'YosysHQ:main' into master 2024-08-06 01:01:08 -07:00
Miodrag Milanovic
d08bf671b2 Next dev cycle 2024-08-06 09:48:35 +02:00
Miodrag Milanovic
80ba43d262 Release version 0.44 2024-08-06 09:42:28 +02:00
Miodrag Milanović
e5d8505349
Merge pull request #4523 from YosysHQ/emil/no-lto-lld 
Makefile: no LTO and lld by default
 2024-08-06 09:08:09 +02:00
github-actions[bot]
d2b5788674 Bump version 2024-08-06 00:18:14 +00:00
Akash Levy
24f38678ac NDEBUG doesn't do anything 2024-08-05 16:46:00 -07:00
Akash Levy
b4ae5e8574
Merge branch 'YosysHQ:main' into master 2024-08-05 11:02:17 -07:00
Emil J. Tywoniak
eeecb54532 Makefile: no LTO and lld by default 2024-08-05 19:28:09 +02:00
N. Engelhardt
01b99972b4
Merge pull request #4518 from YosysHQ/micko/sim_signal_names 
Set ranges on exported wires in VCD and FST
 2024-08-05 15:03:59 +02:00
Miodrag Milanovic
6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Akash Levy
f7ffd73fa0 Fix opt_dff problem 2024-08-01 09:20:18 -07:00
Akash Levy
76db4e390b Smalledit 2024-08-01 00:04:50 -07:00
Akash Levy
9873315caa Update Verific 2024-07-31 22:40:15 -07:00