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4812 commits 122 branches 59 tags 73 MiB
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Author SHA1 Message Date
Russell L Friesenhahn
ee620c6a24 Relax test to see if yosys dir is a git repository in Makefile 
This prevents the test from failing in the case that yosys is a
submodule of a repository since for a submodule the .git is actually a
file containing the location of the submodule's .git directory
 2016-08-26 11:15:36 -05:00
Russell L Friesenhahn
23f217b166 Allow redefining of the ABC repository URL 
For persons or organizations that prefer to keep their own mirrors of
repositories, users may now specify the URL of the ABC Mercurial
repository that yosys clones during build.

The URL may be set in the Makefile directly, on the
command-line, or in the environment
 2016-08-26 11:14:24 -05:00
Clifford Wolf
17233b11e1 Various fixes and improvements in smt2 back-end 2016-08-26 17:33:02 +02:00
Clifford Wolf
4be4969bae Improved verilog parser errors 2016-08-25 11:44:37 +02:00
Clifford Wolf
ad56ad44c3 More yosys-smtbmc smtc features 2016-08-24 23:18:29 +02:00
Clifford Wolf
ee3e7a0e45 yosys-smtbmc --smtc -g 2016-08-24 22:09:50 +02:00
Clifford Wolf
cd18235f30 Added SV "restrict" keyword 2016-08-24 15:30:08 +02:00
Clifford Wolf
6523023645 Minor yosys-smtbmc bugfix 2016-08-22 17:45:01 +02:00
Clifford Wolf
583ceee6eb Added "yosys-smtbmc --constr" 2016-08-22 17:27:43 +02:00
Clifford Wolf
2bd30e2026 Added "yosys-smtbmc --dump-constr" 2016-08-22 16:48:46 +02:00
Clifford Wolf
f8a77abfac Added glob support to all front-ends 2016-08-22 15:05:57 +02:00
Clifford Wolf
450f6f59b4 Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
Clifford Wolf
cad40fc874 Fixed bug in memory_share for memory ports with different ABITS 2016-08-22 14:26:33 +02:00
Clifford Wolf
7a33b9892a yosys-smtbmc: improved --dump-vlogtb handling of memories 2016-08-21 15:56:22 +02:00
Clifford Wolf
cdd0b85e47 Added another mem2reg test case 2016-08-21 13:45:46 +02:00
Clifford Wolf
82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf
dbdd8927e7 Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() 2016-08-21 13:18:09 +02:00
Clifford Wolf
a93fcec93f Added examples/smtbmc/demo2.v 2016-08-20 18:44:27 +02:00
Clifford Wolf
f7578b0239 Added "yosys-smtbmc --dump-vlogtb" 2016-08-20 18:43:39 +02:00
Clifford Wolf
ed785194de Added support for memories to smtio.py 2016-08-20 18:42:32 +02:00
Clifford Wolf
c325bae792 Deprecated "write_smt2 -regs" (by default on now), and some other smt2 back-end improvements 2016-08-20 18:41:57 +02:00
Clifford Wolf
28271e43c9 Added "yosys-smtbmc -g" 2016-08-20 16:32:50 +02:00
Clifford Wolf
a889acb897 Added smtbmc longopt support 2016-08-20 16:07:59 +02:00
Clifford Wolf
fe9315b7a1 Fixed finish_addr handling in $readmemh/$readmemb 2016-08-20 13:47:46 +02:00
Clifford Wolf
75bf7416f0 Bugfix in partial mem write handling in verilog back-end 2016-08-20 13:06:06 +02:00
Clifford Wolf
d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf
f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf
9b8e06bee1 Added missing support for mem read enable ports to verilog back-end 2016-08-18 21:47:02 +02:00
Clifford Wolf
b3a01451a5 Bugfix in test_autotb 2016-08-18 13:43:12 +02:00
Clifford Wolf
de8ee412c3 Improved smtbmc vcd generation performance 2016-08-18 11:17:45 +02:00
Clifford Wolf
dfcd30ea86 Added printing of code loc of failed asserts to yosys-smtbmc 2016-08-17 20:10:02 +02:00
Clifford Wolf
42a971226b Fixed default build config 2016-08-16 22:44:38 +02:00
Clifford Wolf
1419f3983e Merge pull request #203 from cr1901/master 
Add MSYS2-compatible build.
 2016-08-16 22:41:53 +02:00
William D. Jones
5299b17056 Add MSYS2-compatible build. 2016-08-16 14:41:59 -04:00
Clifford Wolf
5767e4bc4d Use _Exit(0) on win32, always use _Exit(1) in log_error() 2016-08-16 09:38:54 +02:00
Clifford Wolf
5531bd7578 Updated ABC to hg rev a86455b00da5 2016-08-16 09:08:26 +02:00
Clifford Wolf
00f29d5e5c Fixed use-after-free dict<> usage pattern in hierarchy.cc 2016-08-16 09:07:13 +02:00
Clifford Wolf
b4d544f0d9 Updated ABC to hg rev 760ba358e790 2016-08-16 00:56:42 +02:00
Clifford Wolf
4561586eed ABC mxe cross-build fix 2016-08-16 00:52:10 +02:00
Clifford Wolf
321e15b0bf Minor fixes in show command 2016-08-16 00:36:24 +02:00
Clifford Wolf
5d90a5b905 Added greenpak4_dffinv 2016-08-15 09:33:06 +02:00
Clifford Wolf
f0a8713fea Fixed upto handling in verilog back-end 2016-08-15 08:26:20 +02:00
Clifford Wolf
1058660ac8 Merge pull request #200 from azonenberg/master 
Updates to GP_RCOSC, new GP_DFF*I cells
 2016-08-14 15:49:08 +02:00
Andrew Zonenberg
0b0ba96488 greenpak4: Changed name of inverted output ports for consistency 2016-08-14 00:30:45 -07:00
Andrew Zonenberg
3b9756c6a3 greenpak4: Added GP_DFFxI cells 2016-08-14 00:11:44 -07:00
Andrew Zonenberg
2b062c48cb greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) 2016-08-13 22:27:58 -07:00
Clifford Wolf
6ac67eac10 Merge pull request #198 from whitequark/master 
synth_greenpak4: use attrmvcp to move LOC from wires to cells
 2016-08-11 11:17:44 +02:00
whitequark
0515809448 synth_greenpak4: use attrmvcp to move LOC from wires to cells. 2016-08-10 20:09:35 +00:00
Clifford Wolf
e9fe57c75e Only allow posedge/negedge with 1 bit wide signals 2016-08-10 19:32:11 +02:00