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Author	SHA1	Message	Date
Eddie Hung	fb062c3426	Add comment	2019-07-13 00:52:21 -07:00
Eddie Hung	41243a53b3	Update test with more accurate LUT mask	2019-07-12 21:00:59 -07:00
Eddie Hung	e9bdc86c0e	duplicate -> clone	2019-07-12 19:33:02 -07:00
Eddie Hung	be0cb7f4b8	More cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	7d583f9e57	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	83f23a24a8	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	1adbfb5533	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	39a7c7c54c	More cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	91c07be196	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	399e1ec870	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	58dbb28fd3	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	7dc15bdd2d	Do not double count cells in abc	2019-07-12 08:22:26 -07:00
Clifford Wolf	463f710066	Merge pull request #1183 from whitequark/ice40-always-relut ... synth_ice40: switch -relut to be always on	2019-07-12 10:48:00 +02:00
Eddie Hung	7a912f22b2	Use Const::from_string() not its constructor...	2019-07-12 01:32:10 -07:00
Eddie Hung	28274dfb09	Off by one	2019-07-12 01:17:53 -07:00
Eddie Hung	e0e5d7d68e	Fix spacing	2019-07-12 01:15:22 -07:00
Eddie Hung	4de03bd5e6	Remove double push	2019-07-12 01:08:48 -07:00
Eddie Hung	62ac5ebd02	Map to and from this box if -abc9	2019-07-12 00:53:01 -07:00
Eddie Hung	0f5bddcd79	ice40_opt to handle this box and opt back to SB_LUT4	2019-07-12 00:52:31 -07:00
Eddie Hung	a79ff2501e	Add new box to cells_sim.v	2019-07-12 00:52:19 -07:00
Eddie Hung	c6e16e1334	_ABC macro will map and unmap to this new box	2019-07-12 00:51:37 -07:00
Eddie Hung	fc3d74616f	Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box	2019-07-12 00:50:42 -07:00
Eddie Hung	1c9f3fadb9	Add Tsu offset to boxes, and comments	2019-07-11 17:17:26 -07:00
Eddie Hung	d386177e6d	ABC doesn't like negative delays in flop boxes...	2019-07-11 17:09:17 -07:00
Eddie Hung	3ef927647c	Fix FDCE_1 box	2019-07-11 14:25:47 -07:00
Eddie Hung	1ada568134	Revert "$pastQ should be first input" ... This reverts commit 8f9d529929.	2019-07-11 14:23:45 -07:00
Eddie Hung	854333f2af	Propagate INIT attr	2019-07-11 13:55:47 -07:00
Eddie Hung	8f9d529929	$pastQ should be first input	2019-07-11 13:54:40 -07:00
Eddie Hung	021f8e5492	Fix typo	2019-07-11 13:23:07 -07:00
whitequark	b700a4b1c5	synth_ice40: switch -relut to be always on.	2019-07-11 20:18:41 +00:00
whitequark	a8c5f7f41e	synth_ice40: fix help text typo. NFC.	2019-07-11 20:18:41 +00:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Eddie Hung	931adbaf74	Merge pull request #1185 from koriakin/xc-ff-init-vals ... xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 12:55:14 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Eddie Hung	a314565ad4	Short out async box	2019-07-11 10:52:45 -07:00
Eddie Hung	8fef4c3594	Simplify to $__ABC_ASYNC box	2019-07-11 10:52:33 -07:00
Eddie Hung	93fbd56db1	$__ABC_FD_ASYNC_MUX.Q -> Y	2019-07-11 10:25:59 -07:00
Eddie Hung	bd198aa803	Missing debug message	2019-07-11 10:07:14 -07:00
Eddie Hung	237d8651a5	Error out if abc9 not called with -lut or -luts	2019-07-11 09:58:00 -07:00
Eddie Hung	0c3ed73dad	Count $_NOT_ cells turned into $luts	2019-07-11 09:55:14 -07:00
Eddie Hung	33862d0445	WIP for fixing partitioning, temporarily do not partition	2019-07-11 09:22:52 -07:00
Eddie Hung	c0abd18799	Enable &mfs for abc9, even if it only currently works for ice40	2019-07-11 08:49:06 -07:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Eddie Hung	d357431df1	Restore from master	2019-07-10 22:54:39 -07:00
Eddie Hung	f984e0cb34	Another typo	2019-07-10 22:33:35 -07:00
Clifford Wolf	9112850800	Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark ... write_verilog: write RTLIL::Sa aka - as Verilog ?	2019-07-11 07:25:52 +02:00
Clifford Wolf	fd3d5cefad	Merge pull request #1179 from whitequark/attrmap-proc ... attrmap: also consider process, switch and case attributes	2019-07-11 07:23:28 +02:00
Eddie Hung	375fcbe511	abc_flop to also get topologically sorted	2019-07-10 20:26:09 -07:00
Eddie Hung	9f608d6be3	write_verilog with *.v extension	2019-07-10 20:25:59 -07:00
Eddie Hung	ea6ffea2cd	Fix clk_pol for FD*_1	2019-07-10 20:10:20 -07:00