mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-14 04:48:46 +00:00
Code Activity
8736 commits 97 branches 53 tags 41 MiB
Commit graph

6 commits

Author SHA1 Message Date
R. Ou 6a0682f5a0 coolrunner2: Separate and improve buffer cell insertion pass 
The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
 2020-02-16 20:25:46 -08:00
Robert Ou 8fe9cdf364 coolrunner2: Add extraction for TFFs 2018-03-31 02:54:26 -07:00
Robert Ou 36b75dfcb7 coolrunner2: Initial mapping of latches 2017-06-25 23:58:28 -07:00
Robert Ou 4af5baab21 coolrunner2: Initial mapping of DFFs 
All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
 2017-06-25 23:58:28 -07:00
Robert Ou a64b56648d coolrunner2: Initial techmapping for $sop 2017-06-25 23:58:22 -07:00
Robert Ou 6e0fb889fa coolrunner2: Initial commit 2017-06-24 07:22:56 -07:00