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Author SHA1 Message Date
Martin Povišer
314b864205 passes: show: Reuse string parts in generation of portboxes 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
61abca10a3 passes: show: Touch chunk iteration in gen_portbox 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
60318a5cd8 passes: show: Label no_signode flag 
Label the flag and rearrange the control flow a bit.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
8b1f5fba62 passes: show: Simplify wire bit range logic 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
ad149cc42a passes: show: Factor out 'join_label_pieces' 
In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
5848790835 passes: show: Label signed_suffix flag 
To make it easier to follow what's going on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
13700e12e5 passes: show: s/idx/dot_idx/ for readability 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer
e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals 
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
github-actions[bot]
956c4e485a Bump version 2023-01-12 01:17:55 +00:00
N. Engelhardt
692a0fa33b print filename in liberty log_header 2023-01-11 21:31:46 +01:00
Jannis Harder
d6c7aa0e3d sim/formalff: Clock handling for yw cosim 2023-01-11 18:07:16 +01:00
Jannis Harder
7ddec5093f sim: Improvements and fixes for yw cosim 
* Fixed $cover handling
  * Improved sparse memory handling when writing traces
  * JSON summary output
 2023-01-11 18:07:16 +01:00
Jannis Harder
636b9f2705 Support for BTOR witness to Yosys witness conversion 2023-01-11 18:07:16 +01:00
Jannis Harder
3e25e61778 aiger: Use new JSON code for writing aiger witness map files 2023-01-11 18:07:16 +01:00
Jannis Harder
29461ade17 Add json.{h,cc} for pretty printing JSON 
Avoids errors in trailing comma handling, broken indentation and
improper escaping that is common when building JSON by manually
concatenating strings.
 2023-01-11 18:07:16 +01:00
Jannis Harder
dda972a148 sim: New -append option for Yosys witness cosim 
This is needed to support SBY's append option.
 2023-01-11 18:07:16 +01:00
Jannis Harder
2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder
1494cfff00 New kernel/yw.{h,cc} to support reading Yosys witness files 
This contains parsing code as well as generic routines to associate the
hierarchical signals paths within a Yosys witness file to a loaded RTLIL
design, including support for memories.
 2023-01-11 18:07:16 +01:00
Jannis Harder
f6458bab70 sim: Only check formal cells during gclk simulation updates 
This is required for compatibility with non-multiclock formal semantics.
 2023-01-11 18:07:16 +01:00
Jannis Harder
9c6198a827 sim: Internal API to set $initstate 
This is not yet added to any of the simulation drivers.
 2023-01-11 18:07:16 +01:00
Jannis Harder
44b26d5c6d sim: Emit used memory addresses as signals to output traces 
This matches the behavior of smtbmc.

This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
 2023-01-11 18:07:16 +01:00
Jannis Harder
5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef 
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
 2023-01-11 18:07:16 +01:00
Jannis Harder
673ad561b8 smt2: Treat bweqx as xnor 
Without x-bits they are equivalent
 2023-01-11 18:07:16 +01:00
Jannis Harder
62afe61779 smt2: Directly implement bwmux instead of using bwmuxmap 2023-01-11 18:07:16 +01:00
N. Engelhardt
4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen
2e3c08adc4
Merge pull request #3570 from YosysHQ/claire/eqystuff 
Various Changes for EQY
 2023-01-11 16:37:52 +01:00
Claire Xen
843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder
5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
N. Engelhardt
d742d063d4 remove template declaration that stops function from being used 2023-01-11 16:09:05 +01:00
N. Engelhardt
41ce00e82a
Merge pull request #3620 from YosysHQ/gcc48_remove 2023-01-11 16:05:56 +01:00
Miodrag Milanovic
4fc5207b1e Add deprecation info to changelog 2023-01-11 11:23:23 +01:00
Miodrag Milanovic
5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf
6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
YRabbit
d6a1e022e1 gowin: add a new type of PLL - PLLVR 
This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-01-11 11:41:29 +10:00
github-actions[bot]
7b476996df Bump version 2023-01-11 01:16:47 +00:00
Miodrag Milanović
2677569d48
Merge pull request #3616 from YosysHQ/register_error 
Display error instead of assertion when pass exists
 2023-01-10 11:38:57 +01:00
Miodrag Milanović
2b622258a2
Merge pull request #3615 from YosysHQ/qbfsat_cvc5 
qbfsat support for cvc5, fixes #3608
 2023-01-10 11:38:16 +01:00
Miodrag Milanovic
40282576b0 Display error instead of assertion when pass exists 2023-01-09 17:02:56 +01:00
Miodrag Milanovic
e3c0fd8b10 qbfsat support for cvc5, fixes #3608 2023-01-09 16:14:01 +01:00
github-actions[bot]
f2c689403a Bump version 2023-01-05 00:16:46 +00:00
gatecat
7bac1920b2 nexus: Fix BRAM write enable in PDP mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 17:59:36 +01:00
github-actions[bot]
d3216593da Bump version 2023-01-04 00:16:03 +00:00
Miodrag Milanovic
c34d308bbd Next dev cycle 2023-01-03 09:36:13 +01:00
Miodrag Milanovic
e02b7f64bc Release version 0.25 2023-01-03 09:34:45 +01:00
github-actions[bot]
a27a297ebc Bump version 2023-01-03 00:15:41 +00:00
Peter Gadfort
7971154e72 Merge branch 'master' into stat-json-area 2023-01-02 12:46:41 -05:00
Miodrag Milanović
583ab81670
Merge pull request #3606 from YosysHQ/fix_vs 
Remove cache
 2023-01-02 17:47:13 +01:00
Miodrag Milanovic
a935752df6 Remove cache 2023-01-02 17:16:51 +01:00
N. Engelhardt
fcd1c68ab7 add note to help about how to chain commands 2023-01-02 16:10:28 +01:00
Miodrag Milanović
257b41cd1f
Merge pull request #3577 from KrystalDelusion/deprecate_manual 
Deprecate manual
 2023-01-02 16:07:36 +01:00