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passes: show: Fix portbox bit ranges in case of driven signals

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When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
This commit is contained in:
Martin Povišer 2023-01-12 19:10:00 +01:00
parent 956c4e485a
commit e3709ce776
1 changed files with 1 additions and 1 deletions
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2
passes/cmds/show.cc
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@ -272,7 +272,7 @@ struct ShowWorker
std::string repinfo = rep > 1 ? stringf("%dx ", rep) : "";
if (driver) {
log_assert(!net.empty());
label_string += stringf("<s%d> %d:%d - %s%d:%d |", i, pos, pos-c.width+1, repinfo.c_str(), cl, cr);
label_string += stringf("<s%d> %d:%d - %s%d:%d |", i, pos, pos-rep*c.width+1, repinfo.c_str(), cl, cr);
net_conn_map[net].in.insert({stringf("x%d:s%d", idx, i), rep*c.width});
net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
} else