mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity
3291 commits 124 branches 59 tags 44 MiB
Commit graph

3291 commits

This branch
This branch
All branches
Author SHA1 Message Date
Clifford Wolf
41932e8b64 Added ezSAT api support for don't care values in models 2013-06-09 14:21:18 +02:00
Clifford Wolf
b7ba90910d Fixed handling of $_XOR_ in SAT generator 2013-06-09 14:01:50 +02:00
Clifford Wolf
0efde13775 Added sequential solving support to sat_solve 2013-06-09 13:35:46 +02:00
Clifford Wolf
6f330f0132 Set rl_basic_word_break_characters in shell 2013-06-09 11:51:06 +02:00
Clifford Wolf
e52c9aff1b Improved readline tab completion 2013-06-09 01:04:23 +02:00
Clifford Wolf
bf59a28f80 Look for yosys-abc and yosys-svgviewer where the main exe is 2013-06-09 00:07:26 +02:00
Clifford Wolf
6c8a424872 Added "make abc" and "make install-abc" 2013-06-08 23:48:19 +02:00
Clifford Wolf
5a592b3739 Moved cmds from kernel/ to passes/cmds/ 2013-06-08 23:16:36 +02:00
Clifford Wolf
4b7f070b69 Fixed typo is sat_solve help msg 2013-06-08 15:36:32 +02:00
Clifford Wolf
23a7973094 Added support for shifter cells to SAT generator 2013-06-08 15:12:08 +02:00
Clifford Wolf
92f04eab10 Added "cd" and "ls" commands for convenience 2013-06-08 14:45:28 +02:00
Clifford Wolf
1434312fdd Various improvements in sat_solve pass and SAT generator 2013-06-08 14:11:50 +02:00
Clifford Wolf
99957a825f Added -all and -max options to sat_solve 2013-06-08 12:17:30 +02:00
Clifford Wolf
25ae2d4df0 Fixes and improvements in ezSAT library 2013-06-08 12:14:20 +02:00
Clifford Wolf
c681c17038 Improved auto-detection of -show signals in sat_solve 2013-06-08 09:34:36 +02:00
Clifford Wolf
56b593b91c Improved sat generator and sat_solve pass 2013-06-07 14:37:33 +02:00
Clifford Wolf
46fbe9d262 Added SAT generator and simple sat_solve command 2013-06-07 13:59:13 +02:00
Clifford Wolf
3371563f2f Added ezSAT library 2013-06-07 10:38:35 +02:00
Clifford Wolf
c32b918681 Renamed opt_rmunused to opt_clean 2013-06-05 07:07:31 +02:00
Clifford Wolf
29d6ebd961 Implemented technology mapping for multipliers (using array multiplier) 2013-06-03 12:48:44 +02:00
Clifford Wolf
21d9251e52 Added "dump" command (part ilang backend) 2013-06-02 17:53:30 +02:00
Clifford Wolf
5f2c5f9017 Fixed techmap/flatten for positional module arguments 2013-05-26 12:21:17 +02:00
Clifford Wolf
b11d9408d9 Improved log messages generated by hierarchy pass 2013-05-26 12:20:51 +02:00
Clifford Wolf
cc587fb5f3 Added -nodetect option to fsm pass 2013-05-24 15:34:25 +02:00
Clifford Wolf
cc05404128 Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v 2013-05-24 15:15:59 +02:00
Clifford Wolf
66bc46b30b Improved FSM one-hot encoding, added binary encoding 2013-05-24 14:39:19 +02:00
Clifford Wolf
ed0e2f7a6f Added log_assert() api 2013-05-24 14:38:36 +02:00
Clifford Wolf
ccd2a93439 Added log_abort() api 2013-05-24 12:32:06 +02:00
Clifford Wolf
585fcace10 Fixed a gcc vs. clang determinism problem in abc pass 2013-05-23 16:17:23 +02:00
Clifford Wolf
f674150f1c Fixed memory corruption bug in opt_rmunused 2013-05-23 13:19:28 +02:00
Clifford Wolf
cbe423a1fe Only initialize TCL interpreter when needed 2013-05-23 12:56:23 +02:00
Clifford Wolf
375f83c5ec Fixed memory leak in ilang frontend 2013-05-23 12:55:59 +02:00
Clifford Wolf
e04d88cf22 Added missing newline to some error messages 2013-05-23 11:19:33 +02:00
Clifford Wolf
6a38e767ba Added labels to "help -write-tex-command-reference-manual" output 2013-05-23 09:49:37 +02:00
Clifford Wolf
ebb155b2d5 Added support for processes to show command 2013-05-23 09:15:51 +02:00
Clifford Wolf
04996657c8 Fixed show command for constant assignments 2013-05-23 08:22:44 +02:00
Clifford Wolf
3b8882ae49 Some improvements in opt_rmdff 2013-05-23 07:48:18 +02:00
Clifford Wolf
63e6a35ce2 Merge pull request #6 from hansiglaser/master 
added option '-Dname[=definition]' to command 'read_verilog'
 2013-05-19 16:07:55 -07:00
Johann Glaser
10a195c0a1 added option '-Dname[=definition]' to command 'read_verilog' 2013-05-19 17:07:52 +02:00
Clifford Wolf
fbadb54b9b Removed test cases that have been moved to yosys-test. 
https://github.com/cliffordwolf/yosys-tests/
 2013-05-17 15:32:30 +02:00
Clifford Wolf
3ecc314238 Fixed to aggressive x-folding in opt_const 2013-05-17 14:55:18 +02:00
Clifford Wolf
59d0c75b98 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-05-16 16:51:47 +02:00
Clifford Wolf
c5ee2b306a Merge branch 'bugfix' 2013-05-16 16:44:45 +02:00
Clifford Wolf
6cc8e848b6 Fixed synthesis of functions in latched blocks 2013-05-16 16:44:06 +02:00
Clifford Wolf
ff4a1dd06c Improved vcdcd.pl (added -d option) 2013-05-14 09:41:47 +02:00
Clifford Wolf
be8ecd6d16 Some improvements in vcdcd.pl 2013-05-14 08:50:59 +02:00
Clifford Wolf
b56e06d2f5 Added support for verilog === operator 2013-05-07 14:35:40 +02:00
Clifford Wolf
595db0d7b9 Added tcl "yosys -import" command 2013-05-02 15:27:01 +02:00
Clifford Wolf
97f783e668 Improved/simplified TCL bindings 2013-05-01 14:21:03 +02:00
Clifford Wolf
83c743f717 Added support for const cell inputs in techmap 2013-04-27 18:30:29 +02:00