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8038 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
2c18d530ea Call shregmap -tech xilinx_static 2019-06-05 12:28:26 -07:00
Eddie Hung
e473e74565 Revert "Move ff_map back after ABC for shregmap" 
This reverts commit 9b9bd4e19f.
 2019-06-05 11:53:06 -07:00
Eddie Hung
dfe9d95579 Add -tech xilinx_static 2019-06-05 11:14:14 -07:00
Eddie Hung
e1e37db860 Refactor to ShregmapTechXilinx7Static 2019-06-05 11:08:08 -07:00
Eddie Hung
45d1bdf83a shregmap -tech xilinx_dynamic to work -params and -enpol 2019-06-05 10:21:57 -07:00
Eddie Hung
a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065 
Suppress driver-driver conflict warning for unknown cell types
 2019-06-05 09:59:05 -07:00
Eddie Hung
bcc0a5d136 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-05 09:56:57 -07:00
Eddie Hung
b5aff1de04 Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux 2019-06-05 09:56:51 -07:00
Maciej Kurc
03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Clifford Wolf
f15b5e6309
Merge pull request #1066 from YosysHQ/clifford/fix1056 
Remove yosys_banner() from python wrapper init
 2019-06-05 10:37:39 +02:00
Clifford Wolf
b33176dafb Major rewrite of wire selection in setundef -init 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 10:26:48 +02:00
Clifford Wolf
6cc60ffd67 Indent fix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:53:06 +02:00
Clifford Wolf
00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix 
initialize more registers in setundef -init
 2019-06-05 09:50:15 +02:00
Clifford Wolf
4190d7c094 Fix typo in fmcombine log message, fixes #1063 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:26:44 +02:00
Clifford Wolf
8a6f9977f6 Suppress driver-driver conflict warning for unknown cell types, fixes #1065 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:14:12 +02:00
Clifford Wolf
dd3c333c0a Remove yosys_banner() from python wrapper init, fixes #1056 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 08:57:33 +02:00
Eddie Hung
94a5f4e609 Rename shregmap -tech xilinx -> xilinx_dynamic 2019-06-04 14:34:36 -07:00
Eddie Hung
7b186740d3 Add log_assert to ensure no loops 2019-06-04 12:01:25 -07:00
Eddie Hung
1b836c93bb Only toposort builtin and abc types 2019-06-04 11:56:58 -07:00
Eddie Hung
82d41bc2f2 Add space between -D and _ABC 2019-06-04 11:54:08 -07:00
Eddie Hung
f0e93f33cf Add (* abc_flop_q *) to brams_bb.v 2019-06-04 11:53:51 -07:00
Eddie Hung
6cf092641f Fix name clash 2019-06-04 09:56:36 -07:00
Eddie Hung
e260150321 Add mux_map.v for wide mux 2019-06-04 09:51:47 -07:00
Clifford Wolf
1332051f33
Merge pull request #1062 from tux3/patch-1 
README.md: Missing formatting for <tag>
 2019-06-04 14:37:10 +02:00
Tux3
c66d644b66
README.md: Missing formatting for <tag> 2019-06-04 10:45:41 +02:00
Maciej Kurc
b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Eddie Hung
9b9bd4e19f Move ff_map back after ABC for shregmap 2019-06-03 23:43:23 -07:00
Eddie Hung
09b778744d Respect -nocarry 2019-06-03 23:42:30 -07:00
Eddie Hung
5afa42432f Fix pmux2shiftx logic 2019-06-03 23:29:45 -07:00
Eddie Hung
23a73ca624 Merge mistake 2019-06-03 23:19:22 -07:00
Eddie Hung
f81a0ed92e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-03 23:07:08 -07:00
Eddie Hung
1217e47e83
Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map 
Execute techmap and arith_map simultaneously
 2019-06-03 20:23:37 -07:00
Eddie Hung
b6e59741ae Typo 2019-06-03 20:21:41 -07:00
Eddie Hung
02973474df Remove extra newline 2019-06-03 20:04:47 -07:00
Eddie Hung
c9a0bac541 IS_C_INVERTED 2019-06-03 19:45:56 -07:00
Eddie Hung
0ad50332d9 Execute techmap and arith_map simultaneously 2019-06-03 19:36:09 -07:00
Eddie Hung
ebcc85b9b8 Fix `ifndef 2019-06-03 12:37:02 -07:00
Eddie Hung
0092770317 Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) 2019-06-03 12:34:55 -07:00
Eddie Hung
d018cd9fe3 Assert that box_unique_id is indeed unique 2019-06-03 12:33:47 -07:00
Eddie Hung
295bd8d0bf Remove dupe 2019-06-03 12:32:20 -07:00
Eddie Hung
a54822b1bc Skip internal modules when generating box_unique_id 2019-06-03 12:31:23 -07:00
Eddie Hung
257f7ff5f6 When creating new holes cell, inherit parameters too 2019-06-03 12:30:54 -07:00
Eddie Hung
4da25c76b3 Ooopsie 2019-06-03 09:33:42 -07:00
Eddie Hung
9f44a71715 Consistent with xilinx 2019-06-03 09:23:43 -07:00
Maciej Kurc
5739cf5265 Added tests for attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-03 09:25:20 +02:00
Clifford Wolf
36120fcc30 Only support Symbiotic EDA flavored Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-02 10:14:50 +02:00
Eddie Hung
2228cef62f Add flops as blackboxes 2019-05-31 18:11:46 -07:00
Eddie Hung
01f71085f2 Add FD*E_1 -> FD*E techmap rules 2019-05-31 18:11:24 -07:00
Eddie Hung
dea36d4366 Techmap flops before ABC again 2019-05-31 18:10:25 -07:00
Eddie Hung
e3d160a9ca parse_xaiger to cope with flops 2019-05-31 18:06:36 -07:00