mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-26 09:24:37 +00:00
Code Activity
9473 commits 122 branches 59 tags 72 MiB
Commit graph

395 commits

Author SHA1 Message Date
Eddie Hung
592baebd22 xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only 2020-04-22 17:43:25 -07:00
Eddie Hung
7f33a0294b Cleanup use of hard-coded default parameters in light of #1945 2020-04-22 12:02:30 -07:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung
fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
David Shah
1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 
synth_xilinx: add -dsp-multonly
 2020-02-02 14:53:32 +00:00
David Shah
65716c9982 xilinx_dsp: Add multonly scratchpad var to bypass 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-01 15:30:43 +00:00
Eddie Hung
e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung
b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung
6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung
db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung
e17f3f8c63 Consistency 2020-01-17 16:06:20 -08:00
Eddie Hung
ee500b6d8e xilinx_dsp: add parameter defaults 2020-01-17 16:05:10 -08:00
Eddie Hung
4985318263 ice40_dsp: add default values for parameters 2020-01-17 15:37:52 -08:00
Eddie Hung
6692e5d558 ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs 2020-01-17 15:28:02 -08:00
Miodrag Milanovic
3e14ff1667 fixed invalid char 2019-12-25 20:38:48 +01:00
Marcin Kościelnicki
e226a8f7f1 Minor nit fixes 2019-12-25 15:39:40 +01:00
Eddie Hung
1d0ac659ad Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too 2019-12-23 14:40:59 -08:00
Eddie Hung
75acaff6f5 Fix CEA/CEB check 2019-12-23 14:22:13 -08:00
Eddie Hung
edabe73377 Fix checking CE[AB] and for direct connections 2019-12-23 13:41:26 -08:00
Eddie Hung
71cac30309 Support unregistered cascades for A and B inputs 2019-12-23 12:38:18 -08:00
Eddie Hung
d00533eaa8 Add DSP48A* PCOUT -> PCIN cascade support 2019-12-23 11:42:46 -08:00
Marcin Kościelnicki
666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Eddie Hung
36a88be609 ice40_wrapcarry -unwrap to preserve 'src' attribute 2019-12-09 14:28:54 -08:00
Eddie Hung
bbdf2452b3 -unwrap to create $lut not SB_LUT4 for opt_lut 2019-12-09 13:27:09 -08:00
Eddie Hung
500ed9b501 Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 2019-12-09 12:45:22 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Eddie Hung
946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Eddie Hung
a7e0cca480 Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:18 -08:00
Eddie Hung
5897b918b3 ice40_wrapcarry to preserve SB_CARRY's attributes 2019-12-03 14:48:11 -08:00
Eddie Hung
2105ae176a Check for either sign or zero extension for postAdd packing 2019-11-26 22:51:00 -08:00
Marcin Kościelnicki
15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
Sean Cross
82f60ba938 Makefile: don't assume python is called python3 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849 Fix dffmux peepopt init handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5 Move GENERATE_PATTERN macro to separate utility header 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441 Disable left-over log_debug in peepopt_dffmux.pmg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 10:43:47 +02:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00
Eddie Hung
472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments 
Add notes and comments for xilinx_dsp
 2019-10-08 10:53:30 -07:00
Clifford Wolf
4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry 
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
 2019-10-06 12:11:20 +02:00
Eddie Hung
5c68da4150 Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf 2019-10-05 09:27:12 -07:00
Clifford Wolf
10d0bad67e
Update README.md 2019-10-05 18:13:04 +02:00
Eddie Hung
f90a4b1e24 Missed this 2019-10-05 08:57:37 -07:00
Eddie Hung
991c2ca95b Add comment on why we have to match for clock-enable/reset muxes 2019-10-05 08:56:37 -07:00
Eddie Hung
ebb059896a Add note on pattern detector 2019-10-05 08:53:01 -07:00
Miodrag Milanović
7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix 
Fixes for MSVC build
 2019-10-05 07:48:30 +02:00
Eddie Hung
792cd31052 Add comments for xilinx_dsp_cascade 2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0 Improve comments for xilinx_dsp_CREG 2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6 Fix comment 2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b Restore optimisation for sigM.empty() 2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a Retry on fixing TODOs 2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8 Revert "Fix TODOs" 
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
 2019-10-04 22:31:04 -07:00