1850 commits

Author	SHA1	Message	Date
Clifford Wolf	c1cfca8f54	Improve Verific SVA importer	2017-07-27 14:05:09 +02:00
Clifford Wolf	2336d5508b	Add log_warning_noprefix() API, Use for Verific warnings and errors	2017-07-27 12:17:04 +02:00
Clifford Wolf	d9641621d9	Add "verific -import -n" and "verific -import -nosva"	2017-07-27 11:54:45 +02:00
Clifford Wolf	90d8329f64	Improve Verific SVA import: negedge and $past	2017-07-27 11:40:07 +02:00
Clifford Wolf	147ff96ba3	Improve Verific SVA importer	2017-07-27 10:39:39 +02:00
Clifford Wolf	530040ba6f	Improve Verific bindings (mostly related to SVA)	2017-07-26 18:00:01 +02:00
Clifford Wolf	abd3b4e8e7	Improve "help verific" message	2017-07-25 15:13:22 +02:00
Clifford Wolf	6dbe1d4c92	Add "verific -extnets"	2017-07-25 14:53:11 +02:00
Clifford Wolf	c97c92e4ec	Improve "verific -all" handling	2017-07-25 13:33:25 +02:00
Clifford Wolf	41be530c4e	Add "verific -import -d <dump_file"	2017-07-24 13:57:16 +02:00
Clifford Wolf	92d3aad670	Add "verific -import -flatten" and "verific -import -v"	2017-07-24 11:29:06 +02:00
Clifford Wolf	5be535517c	Add "verific -import -k"	2017-07-22 16:16:44 +02:00
Clifford Wolf	2785aaffeb	Improve docs for verific bindings, add simply sby example	2017-07-22 11:58:51 +02:00
Clifford Wolf	36cf18ac4c	Fix "read_blif -wideports" handling of cells with wide ports	2017-07-21 16:21:12 +02:00
Clifford Wolf	26766da343	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
Clifford Wolf	9557fd2a36	Add attributes and parameter support to JSON front-end	2017-07-10 13:17:38 +02:00
Clifford Wolf	4b2d1fe688	Add JSON front-end	2017-07-08 16:40:40 +02:00
Clifford Wolf	28039c3063	Add Verific Release information to log	2017-07-04 20:01:30 +02:00
Clifford Wolf	8f8baccfde	Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"	2017-06-07 12:30:24 +02:00
Clifford Wolf	129984e115	Fix handling of Verilog ~& and ~| operators	2017-06-01 12:43:21 +02:00
Clifford Wolf	e91548b33e	Add support for localparam in module header	2017-04-30 17:20:30 +02:00
Clifford Wolf	f0db8ffdbc	Add support for `resetall compiler directive	2017-04-26 16:09:41 +02:00
Clifford Wolf	088f9c9cab	Fix verilog pre-processor for multi-level relative includes	2017-03-14 17:30:20 +01:00
Clifford Wolf	5b3b5ffc8c	Allow $anyconst, etc. in non-formal SV mode	2017-03-01 10:47:05 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	00dba4c197	Add support for SystemVerilog unique, unique0, and priority case	2017-02-23 16:33:19 +01:00
Clifford Wolf	1e927a51d5	Preserve string parameters	2017-02-23 15:39:13 +01:00
Clifford Wolf	34d4e72132	Added SystemVerilog support for ++ and --	2017-02-23 11:21:33 +01:00
Clifford Wolf	4fb8007171	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	2017-02-14 15:10:59 +01:00
Clifford Wolf	cdb6ceb8c6	Add support for verific mem initialization	2017-02-11 15:57:36 +01:00
Clifford Wolf	c449f4b86f	Fix another stupid bug in the same line	2017-02-11 11:47:51 +01:00
Clifford Wolf	fa4a7efe15	Add verific support for initialized variables	2017-02-11 11:40:18 +01:00
Clifford Wolf	0b7aac645c	Improve handling of Verific warnings and error messages	2017-02-11 11:39:50 +01:00
Clifford Wolf	eb7b18e897	Fix extremely stupid typo	2017-02-11 11:09:07 +01:00
Clifford Wolf	848062088c	Add checker support to verilog front-end	2017-02-09 13:51:44 +01:00
Clifford Wolf	2ca8d483dd	Add "rand" and "rand const" verific support	2017-02-09 12:53:46 +01:00
Clifford Wolf	ef4a28e112	Add SV "rand" and "const rand" support	2017-02-08 14:38:15 +01:00
Clifford Wolf	1d1f56a361	Add PSL parser mode to verific front-end	2017-02-08 10:40:33 +01:00
Clifford Wolf	7e0b776a79	Add "read_blif -wideports"	2017-02-06 14:48:03 +01:00
Clifford Wolf	6abf79eb28	Further improve cover() support	2017-02-04 17:02:13 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	911c44d164	Add assert/assume support to verific front-end	2017-02-04 13:36:00 +01:00
Clifford Wolf	fea528280b	Add "enum" and "typedef" lexer support	2017-01-17 17:33:52 +01:00
Clifford Wolf	78f65f89ff	Fix bug in AstNode::mem2reg_as_needed_pass2()	2017-01-15 13:52:50 +01:00
Clifford Wolf	2d32c6c4f6	Fixed handling of local memories in functions	2017-01-05 13:19:03 +01:00
Clifford Wolf	81a9ee2360	Added handling of local memories and error for local decls in unnamed blocks	2017-01-04 16:03:04 +01:00
Clifford Wolf	dfb461fe52	Added Verilog $rtoi and $itor support	2017-01-03 17:40:58 +01:00
Clifford Wolf	3886669ab6	Added "verilog_defines" command	2016-12-15 17:49:28 +01:00
Clifford Wolf	ecdc22b06c	Added support for macros as include file names	2016-11-28 14:50:17 +01:00
Clifford Wolf	c7f6fb6e17	Bugfix in "read_verilog -D NAME=VAL" handling	2016-11-28 14:45:05 +01:00