Eddie Hung
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5c277c6325
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Fix and test for balanced case
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2019-06-06 14:21:34 -07:00 |
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Eddie Hung
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0a66720f6f
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Fix warnings
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2019-06-06 14:01:42 -07:00 |
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Eddie Hung
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ccdf989025
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Support cascading $pmux.A with $mux.A and $mux.B
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2019-06-06 13:51:22 -07:00 |
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Eddie Hung
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dc7b8c4b94
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More cleanup
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2019-06-06 12:56:34 -07:00 |
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Eddie Hung
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978fda94f6
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Fix spacing
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2019-06-06 12:46:42 -07:00 |
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Eddie Hung
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d2172c6846
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Non chain user check using next_sig
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2019-06-06 12:44:50 -07:00 |
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Eddie Hung
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705388eb24
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Add non exclusive test
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2019-06-06 12:44:06 -07:00 |
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Eddie Hung
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83450a9489
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Move muxpack from passes/techmap to passes/opt
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2019-06-06 12:15:13 -07:00 |
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Eddie Hung
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3dd0682f29
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Update doc
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2019-06-06 12:11:59 -07:00 |
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Eddie Hung
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030f1d30e9
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Add to CHANGELOG
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2019-06-06 12:04:42 -07:00 |
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Eddie Hung
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b8620f7b3d
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One more and tidy up
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2019-06-06 12:03:44 -07:00 |
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Eddie Hung
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5d4eca5a29
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Add a few more special case tests
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2019-06-06 11:59:41 -07:00 |
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Eddie Hung
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3e76e3a6fa
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Add tests, fix for !=
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2019-06-06 11:54:38 -07:00 |
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Eddie Hung
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543dd11c7e
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Missing file
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2019-06-06 11:03:45 -07:00 |
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Eddie Hung
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7bd1c664a6
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Initial adaptation of muxpack from shregmap
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2019-06-06 10:51:02 -07:00 |
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Clifford Wolf
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b894187cf6
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Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
Added support for parsing attributes on port connections.
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2019-06-06 12:34:05 +02:00 |
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David Shah
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30cedaca10
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Merge pull request #1073 from whitequark/ecp5-diamond-iob
ECP5: implement most Diamond I/O buffer primitives
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2019-06-06 11:22:49 +01:00 |
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whitequark
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f3a26730b6
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ECP5: implement all Diamond I/O buffer primitives.
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2019-06-06 10:18:33 +00:00 |
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Clifford Wolf
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e4e1cd6930
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Merge pull request #1071 from YosysHQ/eddie/fix_1070
Fix typo in opt_rmdff causing register to be incorrectly removed
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2019-06-06 06:50:12 +02:00 |
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Clifford Wolf
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50e2dce5e7
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Merge pull request #1072 from YosysHQ/eddie/fix_1069
Error out if no top module given before 'sim'
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2019-06-06 06:49:07 +02:00 |
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Eddie Hung
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fd8ef128bf
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Missing doc for -tech xilinx in shregmap
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2019-06-05 14:21:44 -07:00 |
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Eddie Hung
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dd134914cc
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Error out if no top module given before 'sim'
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2019-06-05 14:16:24 -07:00 |
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Eddie Hung
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feb2ddb52b
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Fix typo in opt_rmdff
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2019-06-05 14:08:14 -07:00 |
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Eddie Hung
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a3a80b755c
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Merge pull request #1067 from YosysHQ/clifford/fix1065
Suppress driver-driver conflict warning for unknown cell types
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2019-06-05 09:59:05 -07:00 |
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Maciej Kurc
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03e0d3a17c
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Fixed memory leak.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-05 10:42:43 +02:00 |
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Clifford Wolf
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f15b5e6309
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Merge pull request #1066 from YosysHQ/clifford/fix1056
Remove yosys_banner() from python wrapper init
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2019-06-05 10:37:39 +02:00 |
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Clifford Wolf
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b33176dafb
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Major rewrite of wire selection in setundef -init
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 10:26:48 +02:00 |
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Clifford Wolf
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6cc60ffd67
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Indent fix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:53:06 +02:00 |
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Clifford Wolf
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00d32eb73d
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Merge pull request #999 from jakobwenzel/setundefInitFix
initialize more registers in setundef -init
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2019-06-05 09:50:15 +02:00 |
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Clifford Wolf
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4190d7c094
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Fix typo in fmcombine log message, fixes #1063
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:26:44 +02:00 |
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Clifford Wolf
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8a6f9977f6
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Suppress driver-driver conflict warning for unknown cell types, fixes #1065
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:14:12 +02:00 |
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Clifford Wolf
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dd3c333c0a
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Remove yosys_banner() from python wrapper init, fixes #1056
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 08:57:33 +02:00 |
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Clifford Wolf
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1332051f33
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Merge pull request #1062 from tux3/patch-1
README.md: Missing formatting for <tag>
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2019-06-04 14:37:10 +02:00 |
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Tux3
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c66d644b66
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README.md: Missing formatting for <tag>
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2019-06-04 10:45:41 +02:00 |
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Maciej Kurc
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b79bd5b3ca
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-04 10:42:42 +02:00 |
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Eddie Hung
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1217e47e83
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Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map
Execute techmap and arith_map simultaneously
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2019-06-03 20:23:37 -07:00 |
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Eddie Hung
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02973474df
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Remove extra newline
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2019-06-03 20:04:47 -07:00 |
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Eddie Hung
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0ad50332d9
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Execute techmap and arith_map simultaneously
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2019-06-03 19:36:09 -07:00 |
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Maciej Kurc
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5739cf5265
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Added tests for attributes
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-03 09:25:20 +02:00 |
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Clifford Wolf
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36120fcc30
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Only support Symbiotic EDA flavored Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-02 10:14:50 +02:00 |
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Maciej Kurc
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a6cadf6318
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Added support for parsing attributes on port connections.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-05-31 14:58:43 +02:00 |
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Clifford Wolf
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90ec2cda42
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Fix "tee" handling of log_streams
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-31 09:28:51 +02:00 |
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Clifford Wolf
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2faa1d0e80
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Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-30 10:04:26 +02:00 |
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Clifford Wolf
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0df8a3b461
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Merge pull request #1057 from mmicko/fix_478
Aded one more load of .conf to support change of prefix
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2019-05-30 09:58:51 +02:00 |
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Miodrag Milanovic
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14bd40cd3d
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Aded one more load of .conf to support change of prefix
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2019-05-29 18:57:03 +02:00 |
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Clifford Wolf
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349c47250a
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Merge pull request #1049 from YosysHQ/clifford/fix1047
Do not use shiftmul peepopt pattern when mul result is truncated
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2019-05-28 19:02:26 +02:00 |
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Clifford Wolf
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8e647901ef
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Merge pull request #1050 from YosysHQ/clifford/wandwor
Refactored wand/wor support
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2019-05-28 17:42:16 +02:00 |
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Clifford Wolf
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cb285e4b87
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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-28 17:17:56 +02:00 |
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Clifford Wolf
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49d641d97f
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Merge pull request #1048 from mmicko/fix_enable_pyosys
Moved pyosys block in Makefile
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2019-05-28 16:52:40 +02:00 |
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Clifford Wolf
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ba2185ead8
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Refactor hierarchy wand/wor handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-28 16:43:25 +02:00 |
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