12 commits

Author	SHA1	Message	Date
Benedikt Tutzer	5864db3c2b	Fixed issue when using a python plugin in the yosys shell	2018-08-20 14:44:03 +02:00
Benedikt Tutzer	d79a2808cf	Python Passes can now be added with the -m option or with the plugin command. There are still issues when run in shell mode, but they can be used just fine in a python script	2018-08-16 16:00:11 +02:00
Benedikt Tutzer	bf7b73acfc	Added Wrappers for: ... -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h	2018-08-13 15:18:46 +02:00
Benedikt Tutzer	416946a16a	Saving id and pointer to c++ object. Object is valid only if both id and pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more	2018-08-01 10:57:57 +02:00
Benedikt Tutzer	79d7e608cf	Setup is called automatically when the module is loaded, shutdown when python exits	2018-08-01 10:57:46 +02:00
Benedikt Tutzer	57d2197703	Cleaned up comments	2018-08-01 10:57:41 +02:00
Benedikt Tutzer	0371519c39	Added Monitor class that can monitor all changes in a Design or in a Module	2018-07-10 12:51:02 +02:00
Benedikt Tutzer	da8083dbd0	commands can now be run on arbitrary designs, not only on the active one	2018-07-09 16:01:56 +02:00
Benedikt Tutzer	8ebaeecd83	multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues	2018-07-09 15:48:06 +02:00
Benedikt Tutzer	7911379d4a	Introduced namespace and removed class-prefixes to increase readability	2018-06-28 15:07:21 +02:00
Benedikt Tutzer	ccb4dcd013	changed references from hash-ids to IdString names	2018-06-28 14:44:28 +02:00
Benedikt Tutzer	a27fa1833e	added wrappers for Design, Modules, Cells and Wires	2018-06-25 17:08:29 +02:00