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Author	SHA1	Message	Date
Clifford Wolf	583636f0ad	Added BTOR backend README file	2014-02-05 18:31:10 +01:00
Clifford Wolf	f6e6e9b844	Added selection support for r: and selection with relational operators	2014-02-05 18:24:45 +01:00
Clifford Wolf	3b5c462273	presentation progress	2014-02-05 15:06:13 +01:00
Clifford Wolf	9f6364c1c4	presentation progress	2014-02-05 13:12:50 +01:00
Clifford Wolf	aa8e754ae5	Added read_verilog -setattr	2014-02-05 11:22:10 +01:00
Clifford Wolf	5bf33de24a	Added setattr and setparam commands	2014-02-05 11:11:55 +01:00
Clifford Wolf	078cecf9ea	Updated todo items in README file	2014-02-05 01:59:30 +01:00
Clifford Wolf	aa9da46807	Removed old unused files from tests/	2014-02-05 01:55:39 +01:00
Clifford Wolf	968ae31cac	Added support for dump -append	2014-02-04 23:45:30 +01:00
Clifford Wolf	1fb8ba73bd	Throw errors if non-existing selection variables are used	2014-02-04 23:31:06 +01:00
Clifford Wolf	b1bf55dd63	Added select -none	2014-02-04 23:23:44 +01:00
Clifford Wolf	e0c867db53	presentation progress	2014-02-04 23:00:48 +01:00
Clifford Wolf	99b9c56da1	Fixed detection of init attribute in opt_rmdff	2014-02-04 23:00:32 +01:00
Clifford Wolf	69e867f3e8	Added support for inline commands to abc -script	2014-02-04 22:01:53 +01:00
Clifford Wolf	03d63dd861	presentation progress	2014-02-04 16:51:12 +01:00
Clifford Wolf	7a5f378bae	Added hierarchy -purge_lib option	2014-02-04 16:50:13 +01:00
Clifford Wolf	7a66b38c3e	Added test cases for sat command	2014-02-04 13:43:34 +01:00
Clifford Wolf	6891fd79a3	added sat -falsify	2014-02-04 13:34:37 +01:00
Clifford Wolf	d267bcde4e	Fixed bug in sequential sat proofs and improved handling of asserts	2014-02-04 12:46:16 +01:00
Clifford Wolf	ecdf1f5577	Improved handling of reg init in opt_share and opt_rmdff	2014-02-04 12:02:47 +01:00
Clifford Wolf	9e938aa32a	presentation progress	2014-02-04 00:57:11 +01:00
Clifford Wolf	6c3d767976	presentation progress	2014-02-03 16:26:27 +01:00
Clifford Wolf	9e35021585	Addred sat option -ignore_unknown_cells	2014-02-03 16:26:10 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	de9226a64f	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	2014-02-03 13:00:55 +01:00
Clifford Wolf	de336d93b2	More opt_const -mux_bool features	2014-02-02 22:41:24 +01:00
Clifford Wolf	982c9da011	presentation progress	2014-02-02 22:26:26 +01:00
Clifford Wolf	9d0b69edaa	Added opt_const -mux_bool	2014-02-02 22:11:08 +01:00
Clifford Wolf	bee4450c4c	Added support for inverter chains to opt_const	2014-02-02 21:46:42 +01:00
Clifford Wolf	f9c4d33909	Added RTLIL::SigSpec::to_single_sigbit()	2014-02-02 21:35:26 +01:00
Clifford Wolf	67b0ce2578	Only generate write-enable $and if WE is not constant 1 in memory_map	2014-02-02 21:27:26 +01:00
Clifford Wolf	83fa652820	Added constant-clock case to opt_rmdff	2014-02-02 21:09:08 +01:00
Clifford Wolf	6983d3f10b	presentation progress	2014-02-02 17:57:14 +01:00
Clifford Wolf	aa732b0c73	Added show -notitle option	2014-02-02 17:55:32 +01:00
Clifford Wolf	9808acdc75	Added delete command	2014-02-02 17:11:19 +01:00
Clifford Wolf	a9e2d86f86	Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax	2014-02-02 16:47:17 +01:00
Clifford Wolf	0f88e28693	presentation progress	2014-02-02 13:30:49 +01:00
Clifford Wolf	9334c34170	presentation progress	2014-02-02 13:06:28 +01:00
Clifford Wolf	cdd6e11af5	Added support for blanks after -I and -D in read_verilog	2014-02-02 13:06:21 +01:00
Clifford Wolf	f4f0bd6eef	Fixed a bug in miter command	2014-02-01 22:53:27 +01:00
Clifford Wolf	374674aff4	Added sat -show-inputs and -show-outputs	2014-02-01 22:52:44 +01:00
Clifford Wolf	caf540d1ad	Added show -color support for cells and finished show -label implementation	2014-02-01 18:23:32 +01:00
Clifford Wolf	af325bf206	Fixed comment/eol parsing in ilang frontend	2014-02-01 17:28:02 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	1e2440e7ed	Added note about SystemVerilog assert statement to README	2014-02-01 13:04:49 +01:00
Clifford Wolf	fa92722358	Added miter command	2014-02-01 10:35:56 +01:00
Clifford Wolf	1c8f6f21b4	Progress on presentation	2014-01-31 12:48:31 +01:00
Clifford Wolf	ed8ad99960	More changes to techlibs/common/simlib.v for LEC	2014-01-31 11:21:29 +01:00
Clifford Wolf	36a808c572	presentation progress	2014-01-30 15:25:09 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00