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Code Activity
9564 commits 122 branches 59 tags 43 MiB
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1071 commits

Author SHA1 Message Date
Eddie Hung
ec25394808 Rename abc9.cc -> abc9_techmap.cc 2019-12-28 03:16:28 -08:00
Marcin Kościelnicki
a24596def3 iopadmap: Emit tristate buffers with const OE for some edge cases. 2019-12-25 17:37:58 +01:00
Eddie Hung
509070f82f Disable clock domain partitioning in Yosys pass, let ABC do it 2019-12-23 08:36:20 -08:00
Eddie Hung
1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung
979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung
3b559de6e9 Interpret "abc9 -lut" as lut string only if [0-9:] 2019-12-18 12:21:12 -08:00
Eddie Hung
c9c77a90b3 Remove &verify -s 2019-12-17 16:11:54 -08:00
Eddie Hung
b1b99e421e Use pool<> instead of std::set<> to preserver ordering 2019-12-17 16:10:40 -08:00
N. Engelhardt
c8bc1793a4 check scratchpad variable abc9.scriptfile 2019-12-17 19:39:55 +01:00
Eddie Hung
d9bf7061cd Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop 2019-12-16 16:49:48 -08:00
N. Engelhardt
91f427d719 check scratchpad variables for custom abc scripts 2019-12-13 12:54:52 +01:00
Eddie Hung
abf99d4dae tribuf: set scratchpad boolean 'tribuf.added_something' 2019-12-12 14:32:29 -08:00
Eddie Hung
a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung
ab667d3d47 Call abc9 with "&write -n", and parse_xaiger() to cope 2019-12-06 16:35:57 -08:00
Eddie Hung
fce527f4f7 Fix abc9 re-integration, remove abc9_control_wire, use cell->type as 
as part of clock domain for mergeability class
 2019-12-06 16:20:18 -08:00
Eddie Hung
01a3cc29ba abc9 to do clock partitioning again 2019-12-05 17:26:22 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Eddie Hung
d66d06b91d Add assertion 2019-12-03 19:21:42 -08:00
Eddie Hung
a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung
6398b7c17c Cleanup 2019-12-01 23:43:28 -08:00
David Shah
e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Eddie Hung
6831510f5b Fix debug 2019-11-25 12:59:34 -08:00
Eddie Hung
d087024caf Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-25 12:42:09 -08:00
Eddie Hung
180cb39395 abc9 to contain time call 2019-11-25 12:35:57 -08:00
Eddie Hung
f50b6422b0 abc9 to no longer to clock partitioning, operate on whole modules only 2019-11-25 12:35:38 -08:00
Marcin Kościelnicki
6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Eddie Hung
bf1167bc64 Conditioning abc9 on POs not accurate due to cells 2019-11-23 10:26:55 -08:00
Eddie Hung
1851f4b488 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 23:01:18 -08:00
Eddie Hung
900c806d4e Move clkpart into passes/hierarchy 2019-11-22 17:25:53 -08:00
Eddie Hung
bf7d36627e Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4 Only action if there is more than one clock domain 2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4 Replace TODO 2019-11-22 16:58:08 -08:00
Eddie Hung
698854955c Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb Brackets 2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5 Entry in Makefile.inc 2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d New 'clkpart' to {,un}partition design according to clock/enable 2019-11-22 15:35:51 -08:00
Eddie Hung
c4ec42ac38 When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ 
Since they should be captured downwards from the owning flop
 2019-11-21 16:17:03 -08:00
Eddie Hung
729c6b93e8 endomain -> ctrldomain 2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
whitequark
c68722818a flowmap: when doing mincut, ensure source is always in X, not X̅. 
Fixes #1475.
 2019-11-12 00:15:43 +00:00
whitequark
eef32195bd flowmap: don't break if that creates a k+2 (and larger) LUT either. 
Fixes #1405.
 2019-11-11 23:13:00 +00:00
Eddie Hung
2cb2116b4c Use "abc9_period" attribute for delay target 2019-10-07 15:03:44 -07:00
Eddie Hung
3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung
a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8 Fix from merge 2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8 Add temporary abc9 -nomfs and use for synth_xilinx -abc9 2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00