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Code Activity
8036 commits 123 branches 59 tags 44 MiB
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69 commits

Author SHA1 Message Date
Pepijn de Vos
32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7 Fixed tests 2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df don't cound exact luts in big muxes; futile and fragile 2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224 do not use wide luts in testcase 2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964 Add some tests 
Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
 2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a fixed error 2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2 Common memory test now shared 2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9 Remove not needed tests 2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf fix yosys path 2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Eddie Hung
ab7c431905 Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00
David Shah
71b046d639 tests: Check that Icarus can parse arch sim models 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 18:46:22 +01:00