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12531 commits

Author SHA1 Message Date
Miodrag Milanović
acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
2023-05-15 16:34:35 +02:00
Kamil Rakoczy
6b3e6d96a3 Fix missing brackets around else
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2023-05-10 08:09:11 +02:00
github-actions[bot]
d82bae32be Bump version 2023-05-10 00:15:03 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை)
c855502bd5
Update passes/techmap/libparse.cc
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
2023-05-09 06:40:21 -07:00
Miodrag Milanović
7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script
gowin: Add all the primitives.
2023-05-09 11:13:51 +02:00
Miodrag Milanović
5c7cc6ff06
Merge pull request #3745 from rfuest/gowin_alu
gowin: Fix X output of $alu techmap
2023-05-09 11:12:50 +02:00
Miodrag Milanović
226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff
Updated the `plugin` command to better handle paths
2023-05-09 08:46:02 +02:00
Miodrag Milanovic
f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic
9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
github-actions[bot]
0469405abf Bump version 2023-05-09 00:15:34 +00:00
N. Engelhardt
266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt
0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
N. Engelhardt
ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin
5a4e72f57a
Fix sim writeback check for yw_cosim
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
2023-05-08 13:13:09 +12:00
Muthu Annamalai
17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest 2023-05-06 23:37:47 -07:00
YRabbit
8341fd450e Merge branch 'master' into all-primitives-script 2023-05-07 05:58:35 +10:00
Miodrag Milanović
4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop
Synthesizable properties
2023-05-05 11:03:09 +02:00
Muthu Annamalai
d2f3251528 adding unittest 2023-05-04 22:43:04 -07:00
Muthu Annamalai
81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525
- newlines can be allowed in function parsing
2023-05-04 22:30:27 -07:00
YRabbit
4f6a66e257 Merge branch 'master' into all-primitives-script 2023-05-05 10:21:50 +10:00
github-actions[bot]
f93671eb85 Bump version 2023-05-05 00:15:06 +00:00
Jannis Harder
32f5fca2aa
Merge pull request #3694 from daglem/struct-attributes
Handling of attributes for struct / union variables
2023-05-04 22:15:10 +02:00
Dag Lem
fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
Dag Lem
ad437c178d Handling of attributes for struct / union variables
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.

(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.

Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."

    always_ff @(posedge clk) begin
        if (rotate) begin
            { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };

            if (res) begin
                v0.bytes <= '0;
            end else if (w) begin
                v0.bytes[addr] <= data;
            end
        end
    end
2023-05-03 18:44:07 +02:00
Aki Van Ness
bb240665b7
plugin: shuffled the #ifdef WITH_PYTHON's around to un-tangle the code and pulled out the check for the .py extension so it will complain if you try to load a python extension without python support 2023-05-03 03:35:55 -04:00
Aki Van Ness
572c8df9a8
plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with .so.so on the end 2023-05-03 02:22:46 -04:00
Ralf Fuest
30f1d10948 gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
YRabbit
2bab787729 Merge branch 'master' into all-primitives-script 2023-04-26 13:05:20 +10:00
Jannis Harder
7bff8b63b3 rename: Fix renaming cells in -witness mode
This was renaming cells while iterating over them which would always
cause an assertion failure. Apparently having to rename cells to make
all witness signals public is rarely required, so this slipped through.
2023-04-25 12:39:00 +02:00
Jannis Harder
cee3cb31b9
Merge pull request #3734 from jix/fix_unbased_unsized_const
verilog: Fix const eval of unbased unsized constants
2023-04-24 16:08:48 +02:00
github-actions[bot]
51dd029024 Bump version 2023-04-23 00:17:11 +00:00
Benjamin Barzen
8611429237
ABC9: Cell Port Bug Patch (#3670)
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
YRabbit
a1dd794ff8 gowin: Add all the primitives.
Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-22 17:10:53 +10:00
Jannis Harder
3cbca5064c verific: Handle non-seq properties with VerificClocking conditions 2023-04-21 17:19:42 +02:00
Jannis Harder
ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking
This handles conditions on clocked concurrent assertions in unclocked
procedural contexts.
2023-04-21 16:51:42 +02:00
Jannis Harder
985f4926b7 verilog: Fix const eval of unbased unsized constants
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.

This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.

The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
2023-04-20 12:12:50 +02:00
AdamHillier
3861cc31f0 Add outputs before inputs to the sigmap in the AIGER backend. 2023-04-19 11:00:51 +00:00
github-actions[bot]
7efc50367e Bump version 2023-04-19 00:16:35 +00:00
Jannis Harder
88ae463ffe
Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect
Remove a statement without effect.
2023-04-18 10:45:14 +02:00
Henner Zeller
a3a8f7be38 Remove a statement without effect.
The return value of the min(...) call is never used.
Looks like some leftover from some previous implementation.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
2023-04-17 10:53:05 -07:00
github-actions[bot]
a9c792dcee Bump version 2023-04-15 00:16:41 +00:00
Miodrag Milanovic
d0855576ae Next dev cycle 2023-04-14 09:54:46 +02:00
Miodrag Milanovic
0d6f4b0683 Release version 0.28 2023-04-14 09:52:15 +02:00
Miodrag Milanović
b377a39b73
Merge pull request #3727 from YosysHQ/micko/pll_bram
MachXO2: Add PLL and EBR related primitives
2023-04-14 09:34:30 +02:00
github-actions[bot]
a2655a4b70 Bump version 2023-04-13 00:14:37 +00:00
gatecat
e56dad56c4 fabulous: Add support for LUT6s
Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-12 18:42:09 +02:00
YRabbit
f9a6c0fcbd gowin: Add serialization/deserialization primitives
Primitives are added to convert parallel signals to serial and vice versa.

IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-12 09:59:57 +01:00
Miodrag Milanovic
ee3162c58d Add PLL and EBR related primitives 2023-04-10 12:39:09 +02:00
github-actions[bot]
101075611f Bump version 2023-04-07 00:14:38 +00:00
gatecat
266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-06 10:18:48 +01:00