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Author SHA1 Message Date
Eddie Hung
e603d719d6 Fix spacing 2019-07-10 19:04:22 -07:00
Eddie Hung
f3511e4f93 Use \$currQ 2019-07-10 19:01:13 -07:00
Eddie Hung
71acd3ddcf Remove -retime from abc9, revert to abc behav with separate clock/en domains 2019-07-10 18:57:44 -07:00
Eddie Hung
f030be3f1c Preserve all parameters, plus some extra ones for clk/en polarity 2019-07-10 18:57:11 -07:00
Eddie Hung
f8f0ffe786 Small opt 2019-07-10 18:56:50 -07:00
Eddie Hung
4a995c5d80 Change how to specify flops to ABC again 2019-07-10 17:54:56 -07:00
Eddie Hung
a092c48f03 Use split_tokens() 2019-07-10 17:34:51 -07:00
Eddie Hung
3bb48facb2 Remove params from FD*_1 variants 2019-07-10 17:17:54 -07:00
Eddie Hung
0372c900e8 Fix typo, and have !{PRE,CLR} behave as CE 2019-07-10 17:15:49 -07:00
Eddie Hung
7b2599cb94 Move ABC FF stuff to abc_ff.v; add support for other FD* types 2019-07-10 17:06:05 -07:00
Eddie Hung
0ab8f28bc7 Uncomment IS_C_INVERTED parameter 2019-07-10 16:23:15 -07:00
Eddie Hung
838ae1a14c synth_xilinx's map_cells stage to techmap ff_map.v 2019-07-10 16:15:57 -07:00
Eddie Hung
73c8f1a59e Fix box numbering 2019-07-10 16:12:33 -07:00
Eddie Hung
052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Eddie Hung
bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime 
Error out if -abc9 and -retime specified
 2019-07-10 14:38:13 -07:00
Eddie Hung
2f990a7319
Merge pull request #1148 from YosysHQ/xc7mux 
synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
 2019-07-10 14:38:00 -07:00
Eddie Hung
6bbd286e03 Error out if -abc9 and -retime specified 2019-07-10 12:47:48 -07:00
Eddie Hung
58bb84e5b2 Add some spacing 2019-07-10 12:32:33 -07:00
Eddie Hung
521971e32e Add some ASCII art explaining mux decomposition 2019-07-10 12:20:04 -07:00
whitequark
ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Clifford Wolf
c66b4b9131
Merge pull request #1177 from YosysHQ/clifford/async 
Fix clk2fflogic adff reset semantic to negative hold time on reset
 2019-07-10 08:48:20 +02:00
Eddie Hung
e573d024a2 Call muxpack and pmux2shiftx before cmp2lut 2019-07-09 21:26:38 -07:00
Eddie Hung
1122a2e067 Fix first divergence in #1178 2019-07-09 15:49:16 -07:00
Eddie Hung
c55530b901 Restore opt_clean back to original place 2019-07-09 14:29:58 -07:00
Eddie Hung
5b48b18d29 Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6 2019-07-09 14:28:54 -07:00
David Shah
27b27b8781 synth_ecp5: Fix typo in copyright header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-09 22:26:10 +01:00
Clifford Wolf
cae26bf330
Merge pull request #1174 from YosysHQ/eddie/fix1173 
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
 2019-07-09 22:59:51 +02:00
Clifford Wolf
6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position 
write_verilog: fix placement of case attributes
 2019-07-09 22:51:25 +02:00
Clifford Wolf
9546ccdbd3 Fix tests/various/async FFL test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:44:39 +02:00
Clifford Wolf
5138621482 Improve tests/various/async, disable failing ffl test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:21:25 +02:00
Eddie Hung
b1a048a703 Extend using A[1] to preserve don't care 2019-07-09 12:35:41 -07:00
Eddie Hung
f604aa174e
Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc 
Revert "Add "synth -keepdc" option"
 2019-07-09 12:19:40 -07:00
Eddie Hung
bee5d2b21a Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux 2019-07-09 12:16:33 -07:00
whitequark
37bb6b5e96 write_verilog: fix placement of case attributes. NFC. 2019-07-09 19:14:03 +00:00
Eddie Hung
c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Clifford Wolf
c18b23f055 Add tests/various/async.{sh,v} 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:59 +02:00
Clifford Wolf
3dd92fcd15 Improve tests/various/run-test.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:28 +02:00
Clifford Wolf
f8512864cd Add tests/simple_abc9/.gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:01 +02:00
whitequark
6a29e1f5b7 write_verilog: write RTLIL::Sa aka - as Verilog ?. 
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
 2019-07-09 18:35:49 +00:00
Eddie Hung
93522b0ae1 Extend during mux decomposition with 1'bx 2019-07-09 10:59:37 -07:00
Eddie Hung
c864995343 Fix typo and comments 2019-07-09 10:38:07 -07:00
Eddie Hung
00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore 
Rename __builtin_bswap32 -> bswap32
 2019-07-09 10:22:57 -07:00
Eddie Hung
c91cb73562 Merge remote-tracking branch 'origin/master' into xc7mux 2019-07-09 10:22:49 -07:00
Eddie Hung
c68b909210 synth_xilinx to call commands of synth -coarse directly 2019-07-09 10:21:54 -07:00
Eddie Hung
737340327f Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" 
This reverts commit 7f964859ec.
 2019-07-09 10:15:02 -07:00
Eddie Hung
713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Eddie Hung
5a0f2e43c7 Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
Eddie Hung
bc84f7dd10 Fix spacing 2019-07-09 09:22:12 -07:00
Eddie Hung
667199d460 Fix spacing 2019-07-09 09:16:00 -07:00
Clifford Wolf
e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes 
Add support for processes in bugpoint
 2019-07-09 16:59:43 +02:00