806 commits

Author	SHA1	Message	Date
Eddie Hung	0671ae7d79	Merge pull request #1661 from YosysHQ/eddie/abc9_required ... abc9: add support for required times	2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka	34d2fbd2f9	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
Marcin Kościelnicki	b44d0e041f	xilinx: use RAM32M/RAM64M for memories with two read ports ... This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files).	2020-02-02 14:34:21 +01:00
Eddie Hung	c5971cb16c	synth_xilinx: cleanup help	2020-01-28 17:48:43 -08:00
Eddie Hung	0fd64aab25	synth_xilinx: fix help when no active_design; fixes #1664	2020-01-28 17:41:57 -08:00
Marcin Kościelnicki	7e0e42f907	xilinx: Add simulation model for DSP48 (Virtex 4).	2020-01-29 01:40:00 +01:00
Eddie Hung	7939727d14	Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts ... Unpermute LUT ordering for ice40/ecp5/xilinx	2020-01-28 11:55:51 -08:00
Eddie Hung	245b8c4ab6	Fix unresolved conflict from #1573	2020-01-28 10:17:47 -08:00
N. Engelhardt	086c133ea5	Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate ... synth_xilinx: error out if tristate without '-iopad'	2020-01-28 17:24:54 +01:00
Eddie Hung	ce6a690d27	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map ... Now done in read_aiger	2020-01-27 13:30:27 -08:00
Eddie Hung	f2576c096c	Merge branch 'eddie/abc9_refactor' into eddie/abc9_required	2020-01-27 12:29:28 -08:00
Eddie Hung	da134701cd	Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0	2020-01-22 14:22:03 -08:00
Eddie Hung	3d9737c1bd	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	2020-01-21 16:27:40 -08:00
Eddie Hung	5c589244df	Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623	2020-01-17 12:02:46 -08:00
Eddie Hung	1e6d56dca1	+/xilinx/arith_map.v fix $lcu rule	2020-01-17 11:28:37 -08:00
Eddie Hung	b0605128b6	Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required	2020-01-15 16:42:27 -08:00
Eddie Hung	03ce2c72bb	Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor	2020-01-15 16:42:16 -08:00
Miodrag Milanović	abba1541bc	Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W ... synth_xilinx: fix default W value for non-xc7	2020-01-15 08:47:16 +01:00
Eddie Hung	0e4285ca0d	abc9_ops: generate flop box ids, add abc9_required to FD* cells	2020-01-14 15:05:49 -08:00
Eddie Hung	915e7dde73	Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required	2020-01-14 12:57:56 -08:00
Eddie Hung	d21262ee04	Adding (* techmap_autopurge *) to FD* in abc9_map.v	2020-01-14 12:22:21 -08:00
Eddie Hung	36d1a2c60f	synth_xilinx: fix default W value for non-xc7	2020-01-14 11:34:40 -08:00
Miodrag Milanović	9fbeb57bbd	Merge pull request #1623 from YosysHQ/mmicko/edif_attr ... Export wire properties in EDIF	2020-01-14 19:19:32 +01:00
Eddie Hung	f9aae90e7a	Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required	2020-01-12 15:19:41 -08:00
Eddie Hung	35e49fde4d	Another conflict	2020-01-11 18:57:25 -08:00
Eddie Hung	28f814ee59	Add abc9_required to DSP48E1.{A,B,C,D,PCIN}	2020-01-10 17:12:31 -08:00
Eddie Hung	7d94e18100	synth_xilinx: synth_xilinx.abc9.xc7.W to replace XC7_WIRE_DELAY macro	2020-01-10 15:07:46 -08:00
Eddie Hung	475d983676	abc9_ops -prep_times: generate flop boxes from abc9_required attr	2020-01-10 14:49:52 -08:00
Eddie Hung	b2259a9201	Add abc9_ops -check, -prep_times, -write_box for required times	2020-01-10 11:45:41 -08:00
Miodrag Milanovic	992b507537	Use CARRY4 for abc1 as well, preventing issues with Vivado	2020-01-10 12:34:21 +01:00
Eddie Hung	57f6826e29	Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required	2020-01-08 18:30:20 -08:00
Eddie Hung	823a08e0d8	Fix abc9_xc7.box comments	2020-01-07 17:00:38 -08:00
Eddie Hung	6e3e814025	Fix abc9_xc7.box comments	2020-01-07 15:59:18 -08:00
Eddie Hung	94ab3791ce	Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs	2020-01-07 15:44:18 -08:00
Eddie Hung	5c89dead5f	Merge branch 'master' of github.com:YosysHQ/yosys	2020-01-06 16:51:32 -08:00
Eddie Hung	01866a7909	Fix DSP48E1 sim	2020-01-06 16:45:29 -08:00
Eddie Hung	53aa51dc92	Re-enable &mfs for synth_{ecp5,xilinx}	2020-01-06 16:21:04 -08:00
Eddie Hung	98ee8c14df	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-06 15:02:44 -08:00
Eddie Hung	28bf712372	Wrap arrival functions inside `YOSYS too	2020-01-06 11:55:56 -08:00
Eddie Hung	27c150bfcc	Fix return value of arrival time functions, fix word	2020-01-06 11:39:08 -08:00
Eddie Hung	020606f81c	Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required	2020-01-06 09:44:00 -08:00
Eddie Hung	bac1e65a9c	Fix spacing	2020-01-02 17:21:54 -08:00
Eddie Hung	50b68777d3	Drive $[ABCD] explicitly	2020-01-02 13:28:37 -08:00
Eddie Hung	a051801b72	synth_xilinx -dff to work with abc too	2020-01-02 12:53:26 -08:00
Eddie Hung	3012e9eebc	Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor	2020-01-02 12:48:07 -08:00
Eddie Hung	b454735bea	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-02 12:44:06 -08:00
Eddie Hung	ec1756c094	Update comments	2020-01-02 12:39:52 -08:00
Eddie Hung	8e507bd807	abc9 -keepff -> -dff; refactor dff operations	2020-01-02 12:36:54 -08:00
Eddie Hung	d6242be802	Merge pull request #1601 from YosysHQ/eddie/synth_retime ... "abc -dff" to no longer retime by default	2020-01-02 08:46:24 -08:00
Eddie Hung	d0d3ab8f67	ifndef __ICARUS__ -> ifdef YOSYS	2020-01-01 17:33:47 -08:00