5802 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Clifford Wolf	ab28491f27	Added "opt -full" alias for all more aggressive optimizations	2014-10-31 03:36:51 +01:00
Clifford Wolf	a21481b338	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	2014-10-30 14:01:02 +01:00
Clifford Wolf	ac8f4d298b	Improved nomem2reg documentation	2014-10-30 09:12:55 +01:00
Clifford Wolf	269e37e969	Added support for empty lines to here documents	2014-10-29 09:05:17 +01:00
Clifford Wolf	37aa2e02db	AST simplifier: optimize constant AST_CASE nodes before recursively descending	2014-10-29 08:29:51 +01:00
Clifford Wolf	f9c096eeda	Added support for task and function args in parentheses	2014-10-27 13:21:57 +01:00
Clifford Wolf	c4a2b3c1e9	Improvements in $readmem[bh] implementation	2014-10-26 23:29:36 +01:00
Clifford Wolf	70b2efdb05	Added support for $readmemh/$readmemb	2014-10-26 20:33:10 +01:00
Clifford Wolf	26cbe4a4e5	Fixed constant "cond ? string1 : string2" with strings of different size	2014-10-25 18:23:53 +02:00
Clifford Wolf	c5eb5e56b8	Re-introduced Yosys::readsome() helper function ... (f.read() + f.gcount() made problems with lines > 16kB)	2014-10-23 10:58:36 +02:00
Clifford Wolf	750c615e7f	minor indenting corrections	2014-10-19 18:42:03 +02:00
Clifford Wolf	3202ba621c	Merge pull request #40 from parvizp/compile_mac_10.9.2 ... Builds on Mac 10.9.2 with LLVM 3.5.	2014-10-19 18:40:22 +02:00
Parviz Palangpour	de8adb8ec5	Builds on Mac 10.9.2 with LLVM 3.5.	2014-10-19 11:14:43 -05:00
Clifford Wolf	6c1c1e9a07	Improved new_id() for win32	2014-10-18 19:26:03 +02:00
Clifford Wolf	bb631c6f5c	Also look for yosys-abc in parent dir on win32	2014-10-18 19:01:44 +02:00
Clifford Wolf	0471d158d9	Various improvements to version reporting on win32	2014-10-18 19:00:52 +02:00
Clifford Wolf	57cd485236	Disabled READLINE in MXE cross build	2014-10-18 18:21:33 +02:00
Clifford Wolf	41db98ba31	Fixed typo in test_cell	2014-10-18 16:52:06 +01:00
Clifford Wolf	6bcb4f1f45	Fixed shell prompt and proc_self_dirname() for win32	2014-10-18 16:51:50 +01:00
Clifford Wolf	84ffe04075	Fixed various VS warnings	2014-10-18 15:20:38 +02:00
Clifford Wolf	85572b05e5	Create vcxsrc in mxe build "make dist"	2014-10-18 15:17:33 +02:00
Clifford Wolf	b5da3a60e1	Moved yosys-config.in to misc/	2014-10-18 14:15:05 +02:00
Clifford Wolf	c321b419d4	Added notes regarding building in VS	2014-10-17 16:39:24 +02:00
Clifford Wolf	e8a609f0e5	Added vcxproj_files.txt to MXE "make dist"	2014-10-17 16:05:00 +02:00
Clifford Wolf	b3a6f8f530	More win32 (mxe and vs) build fixes	2014-10-17 16:04:59 +02:00
Clifford Wolf	468ae92374	Various win32 / vs build fixes	2014-10-17 14:01:47 +02:00
Clifford Wolf	973d376733	Added genfiles.zip to MXE "make dist"	2014-10-17 12:11:15 +02:00
Clifford Wolf	4df902637a	Various MXE build fixes	2014-10-17 12:04:40 +02:00
William Speirs	31267a1ae8	Header changes so it will compile on VS	2014-10-17 11:41:36 +02:00
William Speirs	fda52f05f2	Wrapped math in int constructor	2014-10-17 11:28:14 +02:00
Clifford Wolf	34caeeb4f3	Fixed a few VS warnings	2014-10-17 06:02:38 +02:00
Clifford Wolf	18cb8b4636	Don't be too smart with $dff cells with "init" attribute on out signal	2014-10-16 11:49:31 +02:00
Clifford Wolf	66eb254fc2	Some cleanups in opt_clean	2014-10-16 11:46:57 +02:00
Clifford Wolf	3838856a9e	Print "SystemVerilog" in "read_verilog -sv" log messages	2014-10-16 10:31:54 +02:00
Clifford Wolf	3be5fa053f	Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects	2014-10-16 00:54:14 +02:00
Clifford Wolf	6b05a9e807	Fixed handling of invalid array access in mem2reg code	2014-10-16 00:44:23 +02:00
Clifford Wolf	82ed814fa1	Replaced log_assert() do { ... } while (0) hack with a static inline function	2014-10-15 20:36:32 +02:00
Clifford Wolf	2355ddf75d	Fixed gcc warning	2014-10-15 02:48:51 +02:00
Clifford Wolf	3445a933a5	Fixed MXE build	2014-10-15 02:43:50 +02:00
Clifford Wolf	8cea352a6a	Merge branch 'win32'	2014-10-15 01:20:14 +02:00
Clifford Wolf	1fc6208ec0	Check for _YOSYS_ in yosys.h	2014-10-15 01:18:31 +02:00
Clifford Wolf	f65e1c309f	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Clifford Wolf	c3e9922b5d	Replaced readsome() with read() and gcount()	2014-10-15 01:12:53 +02:00
Clifford Wolf	cf85aab62f	A few indent fixes	2014-10-15 01:05:08 +02:00
William Speirs	e5b8390f44	Changed from "and" to "&&"	2014-10-15 00:59:22 +02:00
William Speirs	9ee3a4b94f	Changed to explicit heap allocated memory	2014-10-15 00:58:56 +02:00
William Speirs	6433203b39	Wrapped init in std::set constructor	2014-10-15 00:58:05 +02:00
William Speirs	9cb2303799	Made iterators extend std::iterator and added == operator	2014-10-15 00:56:37 +02:00
Clifford Wolf	069521e2d5	Define empty __attribute__ macro for non-gcc, non-clang compilers	2014-10-15 00:56:04 +02:00
William Speirs	0352dbfd65	Fixed log so it will compile under Visual Studio ... - Included an implementation of gettimeofday	2014-10-15 00:48:59 +02:00